Datasheet MCP6041, MCP6042, MCP6043, MCP6044 (Microchip) - 7
| Fabricante | Microchip |
| Descripción | Оperational amplifier (op amp) has a gain bandwidth product of 14 kHz with a low typical operating current of 600 nA and an offset voltage that is less than 3 mV |
| Páginas / Página | 40 / 7 — MCP6041/2/3/4. Note:. 10000. 10k. DD = 5.5V. rrents. CM = VDD. 1000. … |
| Formato / tamaño de archivo | PDF / 1.2 Mb |
| Idioma del documento | Inglés |
MCP6041/2/3/4. Note:. 10000. 10k. DD = 5.5V. rrents. CM = VDD. 1000. rrent. A = +125°C. set C. 100. fset. ) 100. Off. d Of. TA = +85°C. | IOS |. ias and
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MCP6041/2/3/4 Note:
Unless otherwise indicated, T A = +25°C, VDD = +1.4V to +6.0V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 1 M to VL, and CL = 60 pF.
10000 10k 10000 10k V s DD = 5.5V V V DD = 5.5V rrents CM = VDD 1000 rrent u 1k 1000 u 1k C I T B A = +125°C set C 100 100 ) fset 100 ) 100 Off A IB A (p d Of (p 10 10 TA = +85°C | IOS | ias and | IOS | ias an B 1 1 t B put pu In 0.1 0.1 In 0.1 0.1 45 55 65 75 85 95 105 115 125 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Ambient Temperature (°C) Common Mode Input Voltage (V) FIGURE 2-13:
Input Bias, Offset Currents
FIGURE 2-16:
Input Bias, Offset Currents vs. Ambient Temperature. vs. Common Mode Input Voltage.
120 0 130 Gain 100 ) -30 120 °) (dB 80 -60 110 VDD = 5.5V ase ( ain Phase h 60 -90 P 100 p G 40 -120 oop VDD = 1.4V Loo 90 en- 20 -150 en-L p 80 O Op 0 -180 DC Open-Loop Gain (dB) 70 V -20 -210 OUT = 0.1V to VDD – 0.1V 60 1.E- 0.001 1.E- 0.01 1.E- 0.1 1.E1+ 1.E+ 10 1.E+ 100 1.E+ 1k 1.E 10k+ 1.E 1 + 00k 1.E+02 100 1.E+03 1k 1.E+04 10k 1.E+05 100k 03 02 01 00 Freq 01 uen 02 cy (Hz) 03 04 05 Load Resistance (
:
) FIGURE 2-14:
Open-Loop Gain, Phase vs.
FIGURE 2-17:
DC Open-Loop Gain vs. Frequency. Load Resistance.
140 140 RL = 50 k B) 130 d 130 ( in 120 120 Ga VDD = 5.5V p o 110 110 o V -L DD = 1.4V 100 en 100 RL = 50 kΩ 90 90 V DC Open-Loop Gain (dB) DC Op DD = 5.0V VOUT = 0.1V to VDD - 0.1V 80 80 0.00 0.05 0.10 0.15 0.20 0.25 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage Headroom; Power Supply Voltage (V) VDD VOH or VOL VSS (V) FIGURE 2-15:
DC Open-Loop Gain vs.
FIGURE 2-18:
DC Open-Loop Gain vs. Power Supply Voltage. Output Voltage Headroom. 2001-2013 Microchip Technology Inc. DS21669D-page 7 Document Outline 1.0 Electrical Characteristics FIGURE 1-1: Chip Select (CS) Timing Diagram (MCP6043 only). 1.1 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Offset Voltage Drift with TA = -40°C to +85°C. FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 1.4V. FIGURE 2-4: Input Offset Voltage Drift with TA = +85°C to +125°C and VDD = 1.4V. FIGURE 2-5: Input Offset Voltage Drift with TA = +25°C to +125°C and VDD = 5.5V. FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 5.5V. FIGURE 2-7: Input Offset Voltage vs. Output Voltage. FIGURE 2-8: Input Noise Voltage Density vs. Frequency. FIGURE 2-9: CMRR, PSRR vs. Frequency. FIGURE 2-10: The MCP6041/2/3/4 family shows no phase reversal. FIGURE 2-11: Input Noise Voltage Density vs. Common Mode Input Voltage. FIGURE 2-12: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-13: Input Bias, Offset Currents vs. Ambient Temperature. FIGURE 2-14: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-15: DC Open-Loop Gain vs. Power Supply Voltage. FIGURE 2-16: Input Bias, Offset Currents vs. Common Mode Input Voltage. FIGURE 2-17: DC Open-Loop Gain vs. Load Resistance. FIGURE 2-18: DC Open-Loop Gain vs. Output Voltage Headroom. FIGURE 2-19: Channel-to-Channel Separation vs. Frequency (MCP6042 and MCP6044 only). FIGURE 2-20: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature with VDD = 1.4V. FIGURE 2-21: Quiescent Current vs. Power Supply Voltage. FIGURE 2-22: Gain Bandwidth Product, Phase Margin vs. Common Mode Input Voltage. FIGURE 2-23: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature with VDD = 5.5V. FIGURE 2-24: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-25: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-26: Slew Rate vs. Ambient Temperature. FIGURE 2-27: Small Signal Non-inverting Pulse Response. FIGURE 2-28: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-29: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-30: Small Signal Inverting Pulse Response. FIGURE 2-31: Large Signal Non-inverting Pulse Response. FIGURE 2-32: Chip Select (CS) to Amplifier Output Response Time (MCP6043 only). FIGURE 2-33: Input Current vs. Input Voltage (below VSS). FIGURE 2-34: Large Signal Inverting Pulse Response. FIGURE 2-35: Chip Select (CS) Hysteresis (MCP6043 only). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Chip Select Digital Input 3.4 Power Supply Pins 4.0 Applications Information 4.1 Rail-to-Rail Input FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Output Loads and Battery Life 4.4 Capacitive Loads FIGURE 4-3: Output Resistor, RISO Stabilizes Large Capacitive Loads. FIGURE 4-4: Recommended RISO Values for Capacitive Loads. 4.5 MCP6043 Chip Select 4.6 Supply Bypass 4.7 Unused Op Amps FIGURE 4-5: Unused Op Amps. 4.8 PCB Surface Leakage FIGURE 4-6: Example Guard Ring Layout for Inverting Gain. 4.9 Application Circuits FIGURE 4-7: High-Side Battery Current Sensor. FIGURE 4-8: Two Op Amp Instrumentation Amplifier. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 MAPS (Microchip Advanced Part Selector) 5.4 Analog Demonstration and Evaluation Boards 5.5 Application Notes 6.0 Packaging Information 6.1 Package Marking Information Appendix A: Revision History Product Identification System Trademarks Worldwide Sales and Service
Unless otherwise indicated, T A = +25°C, VDD = +1.4V to +6.0V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 1 M to VL, and CL = 60 pF.
10000 10k 10000 10k V s DD = 5.5V V V DD = 5.5V rrents CM = VDD 1000 rrent u 1k 1000 u 1k C I T B A = +125°C set C 100 100 ) fset 100 ) 100 Off A IB A (p d Of (p 10 10 TA = +85°C | IOS | ias and | IOS | ias an B 1 1 t B put pu In 0.1 0.1 In 0.1 0.1 45 55 65 75 85 95 105 115 125 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Ambient Temperature (°C) Common Mode Input Voltage (V) FIGURE 2-13:
Input Bias, Offset Currents
FIGURE 2-16:
Input Bias, Offset Currents vs. Ambient Temperature. vs. Common Mode Input Voltage.
120 0 130 Gain 100 ) -30 120 °) (dB 80 -60 110 VDD = 5.5V ase ( ain Phase h 60 -90 P 100 p G 40 -120 oop VDD = 1.4V Loo 90 en- 20 -150 en-L p 80 O Op 0 -180 DC Open-Loop Gain (dB) 70 V -20 -210 OUT = 0.1V to VDD – 0.1V 60 1.E- 0.001 1.E- 0.01 1.E- 0.1 1.E1+ 1.E+ 10 1.E+ 100 1.E+ 1k 1.E 10k+ 1.E 1 + 00k 1.E+02 100 1.E+03 1k 1.E+04 10k 1.E+05 100k 03 02 01 00 Freq 01 uen 02 cy (Hz) 03 04 05 Load Resistance (
:
) FIGURE 2-14:
Open-Loop Gain, Phase vs.
FIGURE 2-17:
DC Open-Loop Gain vs. Frequency. Load Resistance.
140 140 RL = 50 k B) 130 d 130 ( in 120 120 Ga VDD = 5.5V p o 110 110 o V -L DD = 1.4V 100 en 100 RL = 50 kΩ 90 90 V DC Open-Loop Gain (dB) DC Op DD = 5.0V VOUT = 0.1V to VDD - 0.1V 80 80 0.00 0.05 0.10 0.15 0.20 0.25 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage Headroom; Power Supply Voltage (V) VDD VOH or VOL VSS (V) FIGURE 2-15:
DC Open-Loop Gain vs.
FIGURE 2-18:
DC Open-Loop Gain vs. Power Supply Voltage. Output Voltage Headroom. 2001-2013 Microchip Technology Inc. DS21669D-page 7 Document Outline 1.0 Electrical Characteristics FIGURE 1-1: Chip Select (CS) Timing Diagram (MCP6043 only). 1.1 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Offset Voltage Drift with TA = -40°C to +85°C. FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 1.4V. FIGURE 2-4: Input Offset Voltage Drift with TA = +85°C to +125°C and VDD = 1.4V. FIGURE 2-5: Input Offset Voltage Drift with TA = +25°C to +125°C and VDD = 5.5V. FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 5.5V. FIGURE 2-7: Input Offset Voltage vs. Output Voltage. FIGURE 2-8: Input Noise Voltage Density vs. Frequency. FIGURE 2-9: CMRR, PSRR vs. Frequency. FIGURE 2-10: The MCP6041/2/3/4 family shows no phase reversal. FIGURE 2-11: Input Noise Voltage Density vs. Common Mode Input Voltage. FIGURE 2-12: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-13: Input Bias, Offset Currents vs. Ambient Temperature. FIGURE 2-14: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-15: DC Open-Loop Gain vs. Power Supply Voltage. FIGURE 2-16: Input Bias, Offset Currents vs. Common Mode Input Voltage. FIGURE 2-17: DC Open-Loop Gain vs. Load Resistance. FIGURE 2-18: DC Open-Loop Gain vs. Output Voltage Headroom. FIGURE 2-19: Channel-to-Channel Separation vs. Frequency (MCP6042 and MCP6044 only). FIGURE 2-20: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature with VDD = 1.4V. FIGURE 2-21: Quiescent Current vs. Power Supply Voltage. FIGURE 2-22: Gain Bandwidth Product, Phase Margin vs. Common Mode Input Voltage. FIGURE 2-23: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature with VDD = 5.5V. FIGURE 2-24: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-25: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-26: Slew Rate vs. Ambient Temperature. FIGURE 2-27: Small Signal Non-inverting Pulse Response. FIGURE 2-28: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-29: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-30: Small Signal Inverting Pulse Response. FIGURE 2-31: Large Signal Non-inverting Pulse Response. FIGURE 2-32: Chip Select (CS) to Amplifier Output Response Time (MCP6043 only). FIGURE 2-33: Input Current vs. Input Voltage (below VSS). FIGURE 2-34: Large Signal Inverting Pulse Response. FIGURE 2-35: Chip Select (CS) Hysteresis (MCP6043 only). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Chip Select Digital Input 3.4 Power Supply Pins 4.0 Applications Information 4.1 Rail-to-Rail Input FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Output Loads and Battery Life 4.4 Capacitive Loads FIGURE 4-3: Output Resistor, RISO Stabilizes Large Capacitive Loads. FIGURE 4-4: Recommended RISO Values for Capacitive Loads. 4.5 MCP6043 Chip Select 4.6 Supply Bypass 4.7 Unused Op Amps FIGURE 4-5: Unused Op Amps. 4.8 PCB Surface Leakage FIGURE 4-6: Example Guard Ring Layout for Inverting Gain. 4.9 Application Circuits FIGURE 4-7: High-Side Battery Current Sensor. FIGURE 4-8: Two Op Amp Instrumentation Amplifier. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 MAPS (Microchip Advanced Part Selector) 5.4 Analog Demonstration and Evaluation Boards 5.5 Application Notes 6.0 Packaging Information 6.1 Package Marking Information Appendix A: Revision History Product Identification System Trademarks Worldwide Sales and Service