Datasheet MCP6041, MCP6042, MCP6043, MCP6044 (Microchip) - 6

MCP6041/2/3/4 Note:
Unless otherwise indicated, T  A = +25°C, VDD = +1.4V to +6.0V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 1 M to VL, and CL = 60 pF.
500 6 ) V ) V 5 450 e (µ es ( 4 ltag 400 VDD = 1.4V VIN VOUT o ltag o 3 t V set V 350 u 2 tp Off V t DD = 5.5V u 300 1 t, Ou u Inp p In 0 V 250 DD = 5.0V G = +2 V/V 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -1 Output Voltage (V) 0 5 T 10 ime (5 ms 15 /div) 20 25 FIGURE 2-7:
Input Offset Voltage vs.
FIGURE 2-10:
The MCP6041/2/3/4 family Output Voltage. shows no phase reversal.
1000 300 f = 1 kHz V 250 DD = 5.0V 200 Hz)
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150 (nV/Hz) (nV/ 100 50 Input Noise Voltage Density Input Noise Voltage Density 100 0 0.1 1 10 100 1000 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Frequency (Hz) Common Mode Input Voltage (V) FIGURE 2-8:
Input Noise Voltage Density
FIGURE 2-11:
Input Noise Voltage Density vs. Frequency. vs. Common Mode Input Voltage.
90 100 Referred to Input 80 95 B) d 70 B) d ( 90 PSRR (VCM = VSS) 60 RR ( 85 50 RR, PSRR PSRR– RR, CM 80 40 PSRR+ S CMRR CM CMRR P (VDD = 5.0V, VCM = -0.3V to +5.3V) 30 75 20 70 0.1 1 10 100 1000 -50 -25 0 25 50 75 100 125 Frequency (Hz) Ambient Temperature (°C) FIGURE 2-9:
CMRR, PSRR vs.
FIGURE 2-12:
CMRR, PSRR vs. Ambient Frequency. Temperature. DS21669D-page 6  2001-2013 Microchip Technology Inc. Document Outline 1.0 Electrical Characteristics FIGURE 1-1: Chip Select (CS) Timing Diagram (MCP6043 only). 1.1 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Offset Voltage Drift with TA = -40°C to +85°C. FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 1.4V. FIGURE 2-4: Input Offset Voltage Drift with TA = +85°C to +125°C and VDD = 1.4V. FIGURE 2-5: Input Offset Voltage Drift with TA = +25°C to +125°C and VDD = 5.5V. FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 5.5V. FIGURE 2-7: Input Offset Voltage vs. Output Voltage. FIGURE 2-8: Input Noise Voltage Density vs. Frequency. FIGURE 2-9: CMRR, PSRR vs. Frequency. FIGURE 2-10: The MCP6041/2/3/4 family shows no phase reversal. FIGURE 2-11: Input Noise Voltage Density vs. Common Mode Input Voltage. FIGURE 2-12: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-13: Input Bias, Offset Currents vs. Ambient Temperature. FIGURE 2-14: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-15: DC Open-Loop Gain vs. Power Supply Voltage. FIGURE 2-16: Input Bias, Offset Currents vs. Common Mode Input Voltage. FIGURE 2-17: DC Open-Loop Gain vs. Load Resistance. FIGURE 2-18: DC Open-Loop Gain vs. Output Voltage Headroom. FIGURE 2-19: Channel-to-Channel Separation vs. Frequency (MCP6042 and MCP6044 only). FIGURE 2-20: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature with VDD = 1.4V. FIGURE 2-21: Quiescent Current vs. Power Supply Voltage. FIGURE 2-22: Gain Bandwidth Product, Phase Margin vs. Common Mode Input Voltage. FIGURE 2-23: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature with VDD = 5.5V. FIGURE 2-24: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-25: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-26: Slew Rate vs. Ambient Temperature. FIGURE 2-27: Small Signal Non-inverting Pulse Response. FIGURE 2-28: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-29: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-30: Small Signal Inverting Pulse Response. FIGURE 2-31: Large Signal Non-inverting Pulse Response. FIGURE 2-32: Chip Select (CS) to Amplifier Output Response Time (MCP6043 only). FIGURE 2-33: Input Current vs. Input Voltage (below VSS). FIGURE 2-34: Large Signal Inverting Pulse Response. FIGURE 2-35: Chip Select (CS) Hysteresis (MCP6043 only). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Chip Select Digital Input 3.4 Power Supply Pins 4.0 Applications Information 4.1 Rail-to-Rail Input FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Output Loads and Battery Life 4.4 Capacitive Loads FIGURE 4-3: Output Resistor, RISO Stabilizes Large Capacitive Loads. FIGURE 4-4: Recommended RISO Values for Capacitive Loads. 4.5 MCP6043 Chip Select 4.6 Supply Bypass 4.7 Unused Op Amps FIGURE 4-5: Unused Op Amps. 4.8 PCB Surface Leakage FIGURE 4-6: Example Guard Ring Layout for Inverting Gain. 4.9 Application Circuits FIGURE 4-7: High-Side Battery Current Sensor. FIGURE 4-8: Two Op Amp Instrumentation Amplifier. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 MAPS (Microchip Advanced Part Selector) 5.4 Analog Demonstration and Evaluation Boards 5.5 Application Notes 6.0 Packaging Information 6.1 Package Marking Information Appendix A: Revision History Product Identification System Trademarks Worldwide Sales and Service