Datasheet CD4013B (Texas Instruments) - 4

CD4013B
SCHS023E – NOVEMBER 1998 – REVISED SEPTEMBER 2016
www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
DC supply voltage, V (2) DD –0.5 20 V Input voltage, all inputs –0.5 VDD + 0.5 V DC input current, any one input 10 mA TA = –55°C to 100°C 500 Power dissipation, PD mW TA = 100°C to 125°C(3) 200 Device dissipation per output transistor 100 mW Operating temperature, TA –55 125 °C Storage temperature, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Voltages reference to VSS terminal (3) Derate linearity at 12 mW/°C
6.2 ESD Ratings VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V(ESD) Electrostatic discharge V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN TYP MAX UNIT
Supply voltage 3 18 V VDD = 5 40 tS Data setup time V ns DD = 10 20 VDD = 15 15 VDD = 5 140 tW Clock pulse width V ns DD = 10 60 VDD = 15 40 VDD = 5 3.5 7 fCL Clock input frequency V MHz DD = 10 8 16 VDD = 15 12 24 VDD = 5 15 trCL(1) Clock rise or fall time V µs t DD = 10 10 fCL VDD = 15 5 VDD = 5 180 tW Set or reset pulse width V ns DD = 10 80 VDD = 15 50 (1) If more than one unit is cascaded in a parallel clocked operation, trCL must be made less than or equal to the sum of the fixed propagation delay time at 15 pF and the transistion time of the output driving stage for the estimated capacitive load. 4 Submit Documentation Feedback Copyright © 1998–2016, Texas Instruments Incorporated Product Folder Links: CD4013B Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information 6.5 Electrical Characteristics: Static 6.6 Electrical Characteristics: Dynamic 6.7 Typical Characteristics 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.4 Device Functional Modes 8 Application and Implementation 8.1 Application Information 8.2 Typical Application 8.2.1 Design Requirements 8.2.2 Detailed Design Procedure 8.2.3 Application Curve 9 Power Supply Recommendations 10 Layout 10.1 Layout Guidelines 10.2 Layout Example 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation 11.2 Receiving Notification of Documentation Updates 11.3 Community Resources 11.4 Trademarks 11.5 Electrostatic Discharge Caution 11.6 Glossary 12 Mechanical, Packaging, and Orderable Information