Datasheet CD4013B (Texas Instruments) - 10

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CD4013B
SCHS023E – NOVEMBER 1998 – REVISED SEPTEMBER 2016
www.ti.com 7 Detailed Description 7.1 Overview
The CD4013B device consists of two identical, independent data-type flip-flops. Each flip-flop has independent data, set, reset, and clock inputs and Q and Q outputs. These devices are ideal for data and memory hold functions, including shift register applications, or by connecting Q output to the data input, this device is used for counter and toggle applications. The CD4013B is a positive-edge triggered device, meaning that the logic level present at the D input is transferred to the Q output during the positive-going transition of the clock pulse. Setting or resetting is independent of the clock and is accomplished by a high level on the set or reset line, respectively.
7.2 Functional Block Diagram
VDD 6 SET1 5 2 D1 Q1 3 F/F1 1 CLOCK1 Q1 4 RESET1 8 SET2 9 12 D2 Q2 11 F/F2 13 CLOCK2 Q2 10 RESET2 VSS Copyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
CD4013B has standardized symmetrical output characteristics and a wide operating voltage range from 3 V to 18 V with quiescent current tested at 20 V. This has a medium operation speed –tPHL, tPLH = 30 ns (typical) at 10 V. The operating temperature is from –55°C to 125°C.
7.4 Device Functional Modes
Table 1 lists the functional modes of the CD4013B.
Table 1. Function Table INPUTS OUTPUT (Q) INVERTED OUTPUT (Q) CLOCK SET RESET D
↑ 0 0 0 0 1 ↑ 0 0 1 1 0 ↓ 0 0 X Q0 Q X 0 1 X 0 1 X 1 0 X 1 0 X 1 1 X 1 1 10 Submit Documentation Feedback Copyright © 1998–2016, Texas Instruments Incorporated Product Folder Links: CD4013B Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information 6.5 Electrical Characteristics: Static 6.6 Electrical Characteristics: Dynamic 6.7 Typical Characteristics 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.4 Device Functional Modes 8 Application and Implementation 8.1 Application Information 8.2 Typical Application 8.2.1 Design Requirements 8.2.2 Detailed Design Procedure 8.2.3 Application Curve 9 Power Supply Recommendations 10 Layout 10.1 Layout Guidelines 10.2 Layout Example 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation 11.2 Receiving Notification of Documentation Updates 11.3 Community Resources 11.4 Trademarks 11.5 Electrostatic Discharge Caution 11.6 Glossary 12 Mechanical, Packaging, and Orderable Information