Datasheet AD9625 (Analog Devices) - 3

Data Sheet AD9625 REVISION HISTORY 5/15—Rev. A to Rev. B
Added Figure 68 .. 32 Added AD9625-2.6 ... Throughout Changes to Data Streaming Section; Added Link Setup Change to Figure 1 .. 1 Parameters Section .. 33 Changes to Table 1 .. 4 Changes to Digital Outputs, Timing, and Controls Section and Changes to Table 2 .. 5 Table 15 ... 34 Change to Figure 5 .. 10 Changes to Table 16 and Table 17 ... 35 Added Endnote 1, Table 8 .. 11 Added Table 18 .. 36 Added Endnote 2, Table 9 .. 13 Added Multichip Synchronization Using SYSREF± Timestamp, Added AD9625-2.6 Section ... 24 Six Lane Output Mode, and SYSREF± Setup and Hold IRQ Changes to Figure 61 and Figure 63 ... 27 Sections ... 39 Changes to Table 11 .. 30 Added IRQ Guardband Delays (SYSREF± Setup and Hold) Added Using the ADA4961 Section ... 30 Section .. 40 Added Figure 77; Renumbered Sequentially, Figure 78, Added Using Rising/Falling Edges of CLK to Latch SYSREF± Figure 79, and Figure 80 ... 31 Section .. 41 Changes to Table 12 .. 34 Changes to Configuration Using the SPI Section ... 46 Changes to Low Bandwidth Decimator Section and Table 13 ... 36 Changes to Transfer Register Map Section, Table 26, and Changes to Table 28 .. 54 Table 27 ... 47 Changes to Table 107 .. 69 Changes to Table28, Table 29, and Table 30 .. 48 Changes to Ordering Guide ... 72 Changes to Table 33 and Table 34 ... 49 Changes to Table 53 .. 52
9/14—Rev. 0 to Rev. A
Changes to Table 54 .. 52 Added AD9625-2.5 ... Throughout Changes to Table 58 .. 54 Changes to Features and General Description Sections .. 1 Changes to Table 71 .. 56 Changes to Table 1 .. 4 Changes to Table 79 and Table 80 ... 57 Changes to Table 2 .. 5 Changes to Table 81, Table 82, Table 83, Table 84, Table 85, and Changes to Table 3 .. 6 Table 86 ... 58 Changes to Table 4 .. 7 Changes to Table 89 .. 59 Changes to Figure 3 and Figure 4 ... 8 Changes to Table 92 and Table 93 ... 60 Changes to Table 6 .. 9 Changes to Table 94, Table 97, and Table 98 ... 61 Changes to Pin K4; Figure 5, Table 8, and Table 9 .. 10 Changes to Table 101 and Table 106 ... 62 Added Typical Performance Characteristics Summary and Added Table 107 and Table 108 ... 63 Changes to Typical Performance Characteristics ... 16 Added Table 115 and Table 116 ... 64 Changes to Figure 45, Figure 49, and Figure 50; Added Added Applications Information Section .. 65 Figure 51 to Figure 54 ... 23 Changes to Ordering Guide ... 66 Changes to Gain Threshold Operation Section .. 24 Changes to Analog Input Considerations Section .. 26
5/14—Revision 0: Initial Version
Changes to Digital Downconverters (DDC) Section ... 28 Rev. B | Page 3 of 72 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9625-2.0 AD9625-2.5 AD9625-2.6 EQUIVALENT TEST CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE FAST DETECT GAIN THRESHOLD OPERATION Threshold Operation Threshold Format TEST MODES ANALOG INPUT CONSIDERATIONS DIFFERENTIAL INPUT CONFIGURATIONS USING THE ADA4961 DC COUPLING CLOCK INPUT CONSIDERATIONS Clock Jitter Considerations Clock Duty Cycle Considerations DIGITAL DOWNCONVERTERS (DDC) FREQUENCY SYNTHESIZER AND MIXER NUMERICALLY CONTROLLED OSCILLATOR HIGH BANDWIDTH DECIMATOR LOW BANDWIDTH DECIMATOR DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) Data Streaming Link Setup Parameters 8-Bit/10-Bit Encoder Digital Outputs, Timing, and Controls De-Emphasis PHYSICAL LAYER OUTPUT SCRAMBLER TAIL BITS DDC MODES (SINGLE AND DUAL) CHECKSUM 8-BIT/10-BIT ENCODER CONTROL INITIAL LANE ALIGNMENT SEQUENCE (ILAS) LANE SYNCHRONIZATION Multichip Synchronization Using SYSREF± Timestamp Six Lane Output Mode ADC Output Control Bits on JESD204B Samples SYSREF± Setup and Hold IRQ IRQ Guardband Delays (SYSREF± Setup and Hold) Using Rising/Falling Edges of the CLK to Latch SYSREF± Test Modes JESD204B APPLICATION LAYERS fS × 2, fS × 4, fS × 8 Modes FRAME ALIGNMENT CHARACTER INSERTION THERMAL CONSIDERATIONS POWER SUPPLY CONSIDERATIONS SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP REGISTER Open and Reserved Locations Default Values Logic Levels Transfer Register Map MEMORY MAP REGISTERS APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND RECOMMENDATIONS CLOCK STABILITY CONSIDERATIONS SPI PORT OUTLINE DIMENSIONS ORDERING GUIDE