Datasheet AD9625 (Analog Devices) - 5

Data Sheet AD9625 AC SPECIFICATIONS
AVDD1 = DVDD1 = DRVDD1 = 1.3 V, AVDD2 = DVDD2 = DRVDD2 = 2.5 V, specified maximum sampling, 1.2 V internal reference, AIN = −1.0 dBFS, sample clock input = 1.65 V p-p differential, default SPI settings, unless otherwise noted.
Table 2. Test Conditions/ AD9625-2.0 AD9625-2.5 AD9625-2.6 Parameter Comments Temperature1 Min Typ Max Min Typ Max Min Typ Max Unit
SPEED GRADE 2.0 2.5 2.6 GSPS ANALOG INPUT Full scale Full 1.1 1.2 1.1 V p-p NOISE DENSITY 25°C −149.0 −149.5 −150.0 dBFS/Hz SIGNAL-TO-NOISE RATIO (SNR) fIN = 100 MHz 25°C 59.5 58.3 58.1 dBFS fIN = 500 MHz 25°C 59.4 58.0 58.0 dBFS fIN = 1000 MHz 25°C 59.0 57.6 57.5 dBFS fIN = 1800 MHz Full 55.4 58.2 54.1 57.0 55.0 56.6 dBFS SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 100 MHz 25°C 58.4 57.2 57.0 dBc fIN = 500 MHz 25°C 58.4 57.0 56.9 dBc fIN = 1000 MHz 25°C 58.0 56.5 56.4 dBc fIN = 1800 MHz Full 54.1 57.2 53.1 55.9 53.9 55.6 dBc EFFECTIVE NUMBER OF BITS (ENOB) fIN = 100 MHz 25°C 9.4 9.2 9.2 Bits fIN = 500 MHz 25°C 9.4 9.2 9.2 Bits fIN = 1000 MHz 25°C 9.3 9.1 9.1 Bits fIN = 1800 MHz 25°C 9.2 9.0 8.9 Bits SPURIOUS FREE Including second or DYNAMIC RANGE thrid harmonic (SFDR) fIN = 100 MHz 25°C 80 77 80.5 dBc fIN = 500 MHz 25°C 81 76 79.6 dBc fIN = 1000 MHz 25°C 80 79 77.3 dBc fIN = 1800 MHz Full 67 76 70 77 65 75.4 dBc WORST OTHER SPUR Excluding second or third harmonic fIN = 100 MHz 25°C −80 −77 −81 dBc fIN = 500 MHz 25°C −86 −76 −83 dBc fIN = 1000 MHz 25°C −83 −82 −80 dBc fIN = 1800 MHz Full −85 −73 −78 −70 −78.0 −66.0 dBc TWO-TONE At −7 dBFS per tone INTERMODULATION DISTORTION (IMD) fIN1 = 728.5 MHz, fIN2 = 25°C −82.8 −81.2 −78.3 dBc 731.5 MHz fIN1 = 1805.5 MHz, fIN2 = 25°C −77.6 −76.3 −77.7 dBc 1808.5 MHz 1 Full temperature range is −40°C to +85°C measured at the case (TC). Rev. B | Page 5 of 72 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9625-2.0 AD9625-2.5 AD9625-2.6 EQUIVALENT TEST CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE FAST DETECT GAIN THRESHOLD OPERATION Threshold Operation Threshold Format TEST MODES ANALOG INPUT CONSIDERATIONS DIFFERENTIAL INPUT CONFIGURATIONS USING THE ADA4961 DC COUPLING CLOCK INPUT CONSIDERATIONS Clock Jitter Considerations Clock Duty Cycle Considerations DIGITAL DOWNCONVERTERS (DDC) FREQUENCY SYNTHESIZER AND MIXER NUMERICALLY CONTROLLED OSCILLATOR HIGH BANDWIDTH DECIMATOR LOW BANDWIDTH DECIMATOR DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) Data Streaming Link Setup Parameters 8-Bit/10-Bit Encoder Digital Outputs, Timing, and Controls De-Emphasis PHYSICAL LAYER OUTPUT SCRAMBLER TAIL BITS DDC MODES (SINGLE AND DUAL) CHECKSUM 8-BIT/10-BIT ENCODER CONTROL INITIAL LANE ALIGNMENT SEQUENCE (ILAS) LANE SYNCHRONIZATION Multichip Synchronization Using SYSREF± Timestamp Six Lane Output Mode ADC Output Control Bits on JESD204B Samples SYSREF± Setup and Hold IRQ IRQ Guardband Delays (SYSREF± Setup and Hold) Using Rising/Falling Edges of the CLK to Latch SYSREF± Test Modes JESD204B APPLICATION LAYERS fS × 2, fS × 4, fS × 8 Modes FRAME ALIGNMENT CHARACTER INSERTION THERMAL CONSIDERATIONS POWER SUPPLY CONSIDERATIONS SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP REGISTER Open and Reserved Locations Default Values Logic Levels Transfer Register Map MEMORY MAP REGISTERS APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND RECOMMENDATIONS CLOCK STABILITY CONSIDERATIONS SPI PORT OUTLINE DIMENSIONS ORDERING GUIDE