Datasheet AD9625 (Analog Devices) - 13

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Data Sheet AD9625 Pin No. Mnemonic Type Description
N1 DRVDD1 Power Serial Digital Power Supply (1.3 V). N2 SERDOUT[7]+ Output Lane 7 CML Output Data, True. N3 SERDOUT[6]+ Output Lane 6 CML Output Data, True. N4 SERDOUT[5]+ Output Lane 5 CML Output Data, True. N5 SERDOUT[4]+ Output Lane 4 CML Output Data, True. N6 DRVDD1 Power Serial Digital Power Supply (1.3 V). N7 SERDOUT[3]+ Output Lane 3 CML Output Data, True. N8 SERDOUT[2]+ Output Lane 2 CML Output Data, True. N9 SERDOUT[1]+ Output Lane 1 CML Output Data, True. N10 SERDOUT[0]+ Output Lane 0 CML Output Data, True. N11 DRVDD1 Power Serial Digital Power Supply (1.3 V). N12 VP_BYP Input Voltage Bypass. N13, N14 DRVDD2 Power Power Supply (2.5 V) Reference Clock Divider for SYNCINB±, DIVCLK±. P1 DRVDD1 Power Serial Digital Power Supply (1.3 V). P2 SERDOUT[7]− Output Lane 7 CML Output Data, Complement. P3 SERDOUT[6]− Output Lane 6 CML Output Data, Complement. P4 SERDOUT[5]− Output Lane 5 CML Output Data, Complement. P5 SERDOUT[4]− Output Lane 4 CML Output Data, Complement. P6 DRVDD1 Power Serializer Digital Power Supply (1.30 V). P7 SERDOUT[3]− Output Lane 3 CML Output Data, Complement. P8 SERDOUT[2]− Output Lane 2 CML Output Data, Complement. P9 SERDOUT[1]− Output Lane 1 CML Output Data, Complement. P10 SERDOUT[0]− Output Lane 0 CML Output Data, Complement. P11 DRVDD1 Power Serializer Digital Power Supply (1.30 V). P12 DRGND Ground Digital Driver Ground Supply. This pin connects to the digital driver ground plane. P13 DIVCLK− Output Divide-by-4 Reference Clock LVDS, Complement. P14 DIVCLK+ Output Divide-by-4 Reference Clock LVDS, True. 1 N/A means not applicable.
Table 9. Pin Function Descriptions (By Function)1 Pin No. Mnemonic Type Description
General Power and Ground Supply Pins A1 to A3, A5, A8, A11, B1 to B4, B6, B8 to B11, AGND Ground ADC Analog Ground. These pins connect to the analog B13, B14, C1 to C5, C7, C9, C10, C12, C13, D5, ground plane. D6, D9, D10, E6, E9, E10, E13, E14, F6, F9, F10, F13, G6, G9, G10, G13, H6, H9, H10, H13, H14, J9, J10, J13, K5 to K13, L13, L14 J6 RBIAS_EXT Input Reference Bias. This pin requires an external 10 kΩ resistor connected to ground. Clock Pins F14 CLK+ Input ADC Clock Input, True. G14 CLK− Input ADC Clock Input, Complement. ADC Analog Power and Ground Supplies Pins A6, A13, A14, B7, B12, C8, C11, D8, D11, E8, AVDD2 Power ADC Analog Power Supply (2.50 V). E11, F8, F11, G8, G11, H8, H11, J8, J11 A4, B5, C6, C14, D7, D12 to D14, E7, E12, F7, AVDD1 Power ADC Analog Power Supply (1.30 V). F12, G7, G12, H7, H12, J7, J12 A12 VM_BYP Input Voltage Bypass. A1 to A3, A5, A8, A11, B1 to B4, B6, B8 to B11, AGND Ground ADC Analog Ground. These pins connect to the analog B13, B14, C1 to C5, C7, C9, C10, C12, C13,D5, ground plane. D6, D9, D10, E6, E9, E10, E13, E14, F6, F9, F10, F13, G6, G9, G10, G13, H6, H9, H10, H13, H14, J9, J10, J13, K5 to K13, L13, L14 Rev. B | Page 13 of 72 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9625-2.0 AD9625-2.5 AD9625-2.6 EQUIVALENT TEST CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE FAST DETECT GAIN THRESHOLD OPERATION Threshold Operation Threshold Format TEST MODES ANALOG INPUT CONSIDERATIONS DIFFERENTIAL INPUT CONFIGURATIONS USING THE ADA4961 DC COUPLING CLOCK INPUT CONSIDERATIONS Clock Jitter Considerations Clock Duty Cycle Considerations DIGITAL DOWNCONVERTERS (DDC) FREQUENCY SYNTHESIZER AND MIXER NUMERICALLY CONTROLLED OSCILLATOR HIGH BANDWIDTH DECIMATOR LOW BANDWIDTH DECIMATOR DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) Data Streaming Link Setup Parameters 8-Bit/10-Bit Encoder Digital Outputs, Timing, and Controls De-Emphasis PHYSICAL LAYER OUTPUT SCRAMBLER TAIL BITS DDC MODES (SINGLE AND DUAL) CHECKSUM 8-BIT/10-BIT ENCODER CONTROL INITIAL LANE ALIGNMENT SEQUENCE (ILAS) LANE SYNCHRONIZATION Multichip Synchronization Using SYSREF± Timestamp Six Lane Output Mode ADC Output Control Bits on JESD204B Samples SYSREF± Setup and Hold IRQ IRQ Guardband Delays (SYSREF± Setup and Hold) Using Rising/Falling Edges of the CLK to Latch SYSREF± Test Modes JESD204B APPLICATION LAYERS fS × 2, fS × 4, fS × 8 Modes FRAME ALIGNMENT CHARACTER INSERTION THERMAL CONSIDERATIONS POWER SUPPLY CONSIDERATIONS SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP REGISTER Open and Reserved Locations Default Values Logic Levels Transfer Register Map MEMORY MAP REGISTERS APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND RECOMMENDATIONS CLOCK STABILITY CONSIDERATIONS SPI PORT OUTLINE DIMENSIONS ORDERING GUIDE