Datasheet LTC2270 (Analog Devices) - 7
| Fabricante | Analog Devices |
| Descripción | 16-Bit, 20Msps Low Noise Dual ADC |
| Páginas / Página | 36 / 7 — POWER REQUIREMENTS. The. denotes the specifications which apply over the … |
| Formato / tamaño de archivo | PDF / 593 Kb |
| Idioma del documento | Inglés |
POWER REQUIREMENTS. The. denotes the specifications which apply over the full operating temperature
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LTC2270
POWER REQUIREMENTS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS CMOS Output Modes: Full Data Rate and Double Data Rate
VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.1 1.8 1.9 V IVDD Analog Supply Current DC Input l 89 100 mA Sine Wave Input 89.5 mA IOVDD Digital Supply Current Sine Wave Input, OVDD = 1.2V 2 mA PDISS Power Dissipation DC Input l 160 180 mW Sine Wave Input, OVDD = 1.2V 164 mW
LVDS Output Mode
VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.7 1.8 1.9 V IVDD Analog Supply Current Sine Input, 1.75mA Mode 91 mA Sine Input, 3.5mA Mode l 93 105 mA IOVDD Digital Supply Current Sine Input, 1.75mA Mode 38 mA (0VDD = 1.8V) Sine Input, 3.5mA Mode l 73 82 mA PDISS Power Dissipation Sine Input, 1.75mA Mode 232 mW Sine Input, 3.5mA Mode l 299 337 mW
All Output Modes
PSLEEP Sleep Mode Power 0.5 mW PNAP Nap Mode Power 12 mW PDIFFCLK Power Increase with Differential Encode Mode Enabled 20 mW (No increase for Nap or Sleep Modes)
TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fS Sampling Frequency (Note 10) l 1 20 MHz tL ENC Low Time (Note 8) Duty Cycle Stabilizer Off l 23.5 25 500 ns Duty Cycle Stabilizer On l 2 25 500 ns tH ENC High Time (Note 8) Duty Cycle Stabilizer Off l 23.5 25 500 ns Duty Cycle Stabilizer On l 2 25 500 ns tAP Sample-and-Hold Acquisition Delay Time 0 ns
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate)
tD ENC to Data Delay CL = 5pF (Note 8) l 1.1 1.7 3.1 ns tC ENC to CLKOUT Delay CL = 5pF (Note 8) l 1 1.4 2.6 ns tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l 0 0.3 0.6 ns Pipeline Latency Full Data Rate Mode 6 6 Cycles Double Data Rate Mode 6.5 6.5 Cycles 2270f 7
POWER REQUIREMENTS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS CMOS Output Modes: Full Data Rate and Double Data Rate
VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.1 1.8 1.9 V IVDD Analog Supply Current DC Input l 89 100 mA Sine Wave Input 89.5 mA IOVDD Digital Supply Current Sine Wave Input, OVDD = 1.2V 2 mA PDISS Power Dissipation DC Input l 160 180 mW Sine Wave Input, OVDD = 1.2V 164 mW
LVDS Output Mode
VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.7 1.8 1.9 V IVDD Analog Supply Current Sine Input, 1.75mA Mode 91 mA Sine Input, 3.5mA Mode l 93 105 mA IOVDD Digital Supply Current Sine Input, 1.75mA Mode 38 mA (0VDD = 1.8V) Sine Input, 3.5mA Mode l 73 82 mA PDISS Power Dissipation Sine Input, 1.75mA Mode 232 mW Sine Input, 3.5mA Mode l 299 337 mW
All Output Modes
PSLEEP Sleep Mode Power 0.5 mW PNAP Nap Mode Power 12 mW PDIFFCLK Power Increase with Differential Encode Mode Enabled 20 mW (No increase for Nap or Sleep Modes)
TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fS Sampling Frequency (Note 10) l 1 20 MHz tL ENC Low Time (Note 8) Duty Cycle Stabilizer Off l 23.5 25 500 ns Duty Cycle Stabilizer On l 2 25 500 ns tH ENC High Time (Note 8) Duty Cycle Stabilizer Off l 23.5 25 500 ns Duty Cycle Stabilizer On l 2 25 500 ns tAP Sample-and-Hold Acquisition Delay Time 0 ns
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate)
tD ENC to Data Delay CL = 5pF (Note 8) l 1.1 1.7 3.1 ns tC ENC to CLKOUT Delay CL = 5pF (Note 8) l 1 1.4 2.6 ns tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l 0 0.3 0.6 ns Pipeline Latency Full Data Rate Mode 6 6 Cycles Double Data Rate Mode 6.5 6.5 Cycles 2270f 7