Preliminary Datasheet EPC2102 (Efficient Power Conversion)
| Fabricante | Efficient Power Conversion |
| Descripción | Enhancement-Mode GaN Power Transistor Half Bridge |
| Páginas / Página | 10 / 1 — EPC2102 – Enhancement-Mode GaN Power Transistor Half Bridge. Preliminary … |
| Formato / tamaño de archivo | PDF / 1.4 Mb |
| Idioma del documento | Inglés |
EPC2102 – Enhancement-Mode GaN Power Transistor Half Bridge. Preliminary Specification Sheet. Features:. Applications:
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EPC2102
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EPC2102 – Enhancement-Mode GaN Power Transistor Half Bridge Preliminary Specification Sheet Features:
• 98% System Efficiency at 18 A o 42 VIN to 14 VOUT, 500 kHz o Includes driver, inductor, and output filter • High Frequency Operation • High Density Footprint EPC2102 devices are supplied only in • Low Inductance Package passivated die form with solder balls Pb-Free (RoHS Compliant), Halogen Free Die Size: 6.05 mm x 2.3 mm
Applications:
• High Frequency DC-DC Conversion
Typical System Efficiency 99 98.5 Typical Circuit ) 98 (% y 97.5 c n e 97 ci 96.5 Effi 96 f 95.5 sw=300 kHz fsw=500 kHz 95 0 2 4 6 8 10 12 14 16 18 20 22 24 26 Output Current (A) VIN = 42 V, VOUT = 14 V MAXIMUM RATINGS Parameter Value
Maximum Drain – Source Voltage (VSW to PGND, VIN to VSW) 60 V Maximum Gate – Source Voltage Range (Gate 1 to VSW, Gate 2 to PGND) -4 V < VGS < 6 V Q1 Control FET 23 A Continuous Drain Current, 25 °C, RθJA = 28 (Q1), 28 (Q2) Q2 Sync FET 23 A Q1 Control FET 215 A Maximum Pulsed Drain Current, 25 °C, Tpulse = 300 µs Q2 Sync FET 215 A Optimum Temperature Range -40 °C < TJ < 150 °C Subject to Change without Notice www.epc-co.com COPYRIGHT 2015 Page 1
• 98% System Efficiency at 18 A o 42 VIN to 14 VOUT, 500 kHz o Includes driver, inductor, and output filter • High Frequency Operation • High Density Footprint EPC2102 devices are supplied only in • Low Inductance Package passivated die form with solder balls Pb-Free (RoHS Compliant), Halogen Free Die Size: 6.05 mm x 2.3 mm
Applications:
• High Frequency DC-DC Conversion
Typical System Efficiency 99 98.5 Typical Circuit ) 98 (% y 97.5 c n e 97 ci 96.5 Effi 96 f 95.5 sw=300 kHz fsw=500 kHz 95 0 2 4 6 8 10 12 14 16 18 20 22 24 26 Output Current (A) VIN = 42 V, VOUT = 14 V MAXIMUM RATINGS Parameter Value
Maximum Drain – Source Voltage (VSW to PGND, VIN to VSW) 60 V Maximum Gate – Source Voltage Range (Gate 1 to VSW, Gate 2 to PGND) -4 V < VGS < 6 V Q1 Control FET 23 A Continuous Drain Current, 25 °C, RθJA = 28 (Q1), 28 (Q2) Q2 Sync FET 23 A Q1 Control FET 215 A Maximum Pulsed Drain Current, 25 °C, Tpulse = 300 µs Q2 Sync FET 215 A Optimum Temperature Range -40 °C < TJ < 150 °C Subject to Change without Notice www.epc-co.com COPYRIGHT 2015 Page 1