Datasheet EL7515 (Renesas) - 8

link to page 8 link to page 8 EL7515 The boost converter output voltage is determined by the
Layout Considerations
relationship in Equation 8: The layout is very important for the converter to function properly. Power Ground ( ) and Signal Ground ( ) should  R  V 2 =   + ---- (EQ. 8) be separated to ensure that the high pulse current in the OUT VFB 1 R  1 Power Ground never interferes with the sensitive signals connected to Signal Ground. They should only be connected where VFB slightly changes with VDD. The curve is shown in at one point. this data sheet. The trace connected to pin 8 (FB) is the most sensitive trace.
RC Filter
It needs to be as short as possible and in a “quiet” place, The maximum voltage rating for the VDD pin is 12V and is preferably between PGND or SGND traces. recommended to be about 10V for maximum efficiency to drive the internal MOSFET. The series resistor R In addition, the bypass capacitor connected to the VDD pin 4 in the RC filter connected to V needs to be as close to the pin as possible. DD can be utilized to reduce the voltage. If VO is larger than 10V, then Equation 9 shows: The heat of the chip is mainly dissipated through the SGND pin. Maximizing the copper area around it is preferable. In V – R O 10 (EQ. 9) 4 = ---------- addition, a solid ground plane is always helpful for the EMI IDD performance. where IDD is shown in IDD vs fS curve. Otherwise, R4 can be The demo board is a good example of layout based on these 10 to 51 with C4 = 0.1µF. principles. Please refer to the EL7515 Application Brief for
Thermal Performance
the layout. http://www.intersil.com/data/tb/tb429.pdf The EL7515 uses a fused-lead package, which has a reduced JA of +100°C/W on a four-layer board and +115°C/W on a two-layer board. Maximizing copper around the ground pins will improve the thermal performance. This chip also has internal thermal shut-down set at around +135°C to protect the component. FN7120 Rev 2.00 Page 8 of 9 August 10, 2007