Datasheet TPLD1201 (Texas Instruments) - 10
| Fabricante | Texas Instruments |
| Descripción | Programmable Logic Device With Eight General Purpose Input Or Outputs (GPIOs) |
| Páginas / Página | 67 / 10 — TPLD1201. www.ti.com. FROM. TEST. PARAMETER. (INPUT). (OUTPUT). … |
| Formato / tamaño de archivo | PDF / 2.6 Mb |
| Idioma del documento | Inglés |
TPLD1201. www.ti.com. FROM. TEST. PARAMETER. (INPUT). (OUTPUT). CONDITIONS. MIN. TYP. MAX UNIT. Counter/Delay
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TPLD1201
SCPS287B – NOVEMBER 2023 – REVISED DECEMBER 2024
www.ti.com
TA = 25°C (unless otherwise noted)
FROM TO TEST PARAMETER V (INPUT) (OUTPUT) CONDITIONS CC MIN TYP MAX UNIT
Rising 1.31 1.8V ± 0.09V Falling 1.53 Rising 1.31 tpd Delay 3-bit LUT IN OUT 3.3V ± 0.3V ns Falling 1.53 Rising 1.31 5V ± 0.5V Falling 1.53 Rising 1.53 1.8V ± 0.09V Falling 1.86 Rising 1.53 tpd Delay 4-bit LUT IN OUT 3.3V ± 0.3V ns Falling 1.86 Rising 1.53 5V ± 0.5V Falling 1.86 Rising 1.42 1.8V ± 0.09V Falling 1.44 Rising 1.42 tpd Delay DFF/Latch CLK Q 3.3V ± 0.3V ns Falling 1.44 Rising 1.42 5V ± 0.5V Falling 1.44 Rising 1.58 1.8V ± 0.09V Falling 1.58 Rising 1.58 tpd Delay DFF/Latch nRST/nSET Q 3.3V ± 0.3V ns Falling 1.58 Rising 1.58 5V ± 0.5V Falling 1.58
Counter/Delay
Rising edge of Rising edge of Falling edge 2.21 IN OUT triggered 1.8V ± 0.09V Falling edge of Falling edge of Rising edge 2.01 IN OUT triggered Rising edge of Rising edge of Falling edge 2.21 Counter - IN OUT triggered tpd Delay 3.3V ± 0.3V ns Delay mode Falling edge of Falling edge of Rising edge 2.01 IN OUT triggered Rising edge of Rising edge of Falling edge 2.21 IN OUT triggered 5V ± 0.5V Falling edge of Falling edge of Rising edge 2.01 IN OUT triggered 1.8V ± 0.09V 57.6 Rising edge 3.3V ± 0.3V 61.4 detect 5V ± 0.5V 62.0 1.8V ± 0.09V 56.0 Counter - Edge Rising edge of Falling edge of Falling edge tpw Pulse width 3.3V ± 0.3V 59.6 ns detect mode OUT OUT detect 5V ± 0.5V 60.4 1.8V ± 0.09V 55.9 Both edge 3.3V ± 0.3V 59.7 detect 5V ± 0.5V 60.5 10 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TPLD1201 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Pin Configuration and Functions 5 Specifications 5.1 Absolute Maximum Ratings 5.2 ESD Ratings 5.3 Recommended Operating Conditions 5.4 Thermal Information 5.5 Electrical Characteristics 5.6 Supply Current Characteristics 5.7 Switching Characteristics 5.8 Typical Characteristics 6 Parameter Measurement Information 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 I/O Pins 7.3.2 Connection Mux 7.3.3 Configurable Use Logic Blocks 7.3.3.1 2-Bit LUT Macro-Cell 7.3.3.2 3-Bit LUT Macro-Cell 7.3.3.3 2-Bit LUT or D Flip-Flop or Latch Macro-Cell 7.3.3.4 3-Bit LUT or D Flip-Flop or Latch with Set or Reset Macro-Cell 7.3.3.5 3-Bit LUT or Pipe Delay Macro-cell 7.3.3.6 4-Bit LUT or 8-Bit Counter or Delay Macro-Cell 7.3.4 8-Bit Counters and Delay Generators (CNT/DLY) 7.3.4.1 Delay Mode 7.3.4.2 Edge Detector Mode 7.3.4.3 Reset Counter Mode 7.3.5 Programmable Deglitch Filter or Edge Detector Macro-cell 7.3.6 Selectable Frequency Oscillator 7.3.7 Analog Comparators (ACMP) 7.3.8 Voltage Reference (VREF) 7.4 Device Functional Modes 7.4.1 Power-On Reset 8 Application and Implementation 8.1 Application Information 8.2 Typical Application 8.2.1 Design Requirements 8.2.1.1 Power Considerations 8.2.1.2 Input Considerations 8.2.1.3 Output Considerations 8.2.2 Detailed Design Procedure 8.2.3 Application Curves 8.3 Power Supply Recommendations 8.4 Layout 8.4.1 Layout Guidelines 8.4.2 Layout Example 9 Device and Documentation Support 9.1 Receiving Notification of Documentation Updates 9.2 Support Resources 9.3 Trademarks 9.4 Electrostatic Discharge Caution 9.5 Glossary 10 Revision History 11 Mechanical, Packaging, and Orderable Information 11.1 Packaging Option Addendum 11.2 Tape and Reel Information 11.3 Mechanical Data
SCPS287B – NOVEMBER 2023 – REVISED DECEMBER 2024
www.ti.com
TA = 25°C (unless otherwise noted)
FROM TO TEST PARAMETER V (INPUT) (OUTPUT) CONDITIONS CC MIN TYP MAX UNIT
Rising 1.31 1.8V ± 0.09V Falling 1.53 Rising 1.31 tpd Delay 3-bit LUT IN OUT 3.3V ± 0.3V ns Falling 1.53 Rising 1.31 5V ± 0.5V Falling 1.53 Rising 1.53 1.8V ± 0.09V Falling 1.86 Rising 1.53 tpd Delay 4-bit LUT IN OUT 3.3V ± 0.3V ns Falling 1.86 Rising 1.53 5V ± 0.5V Falling 1.86 Rising 1.42 1.8V ± 0.09V Falling 1.44 Rising 1.42 tpd Delay DFF/Latch CLK Q 3.3V ± 0.3V ns Falling 1.44 Rising 1.42 5V ± 0.5V Falling 1.44 Rising 1.58 1.8V ± 0.09V Falling 1.58 Rising 1.58 tpd Delay DFF/Latch nRST/nSET Q 3.3V ± 0.3V ns Falling 1.58 Rising 1.58 5V ± 0.5V Falling 1.58
Counter/Delay
Rising edge of Rising edge of Falling edge 2.21 IN OUT triggered 1.8V ± 0.09V Falling edge of Falling edge of Rising edge 2.01 IN OUT triggered Rising edge of Rising edge of Falling edge 2.21 Counter - IN OUT triggered tpd Delay 3.3V ± 0.3V ns Delay mode Falling edge of Falling edge of Rising edge 2.01 IN OUT triggered Rising edge of Rising edge of Falling edge 2.21 IN OUT triggered 5V ± 0.5V Falling edge of Falling edge of Rising edge 2.01 IN OUT triggered 1.8V ± 0.09V 57.6 Rising edge 3.3V ± 0.3V 61.4 detect 5V ± 0.5V 62.0 1.8V ± 0.09V 56.0 Counter - Edge Rising edge of Falling edge of Falling edge tpw Pulse width 3.3V ± 0.3V 59.6 ns detect mode OUT OUT detect 5V ± 0.5V 60.4 1.8V ± 0.09V 55.9 Both edge 3.3V ± 0.3V 59.7 detect 5V ± 0.5V 60.5 10 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TPLD1201 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Pin Configuration and Functions 5 Specifications 5.1 Absolute Maximum Ratings 5.2 ESD Ratings 5.3 Recommended Operating Conditions 5.4 Thermal Information 5.5 Electrical Characteristics 5.6 Supply Current Characteristics 5.7 Switching Characteristics 5.8 Typical Characteristics 6 Parameter Measurement Information 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 I/O Pins 7.3.2 Connection Mux 7.3.3 Configurable Use Logic Blocks 7.3.3.1 2-Bit LUT Macro-Cell 7.3.3.2 3-Bit LUT Macro-Cell 7.3.3.3 2-Bit LUT or D Flip-Flop or Latch Macro-Cell 7.3.3.4 3-Bit LUT or D Flip-Flop or Latch with Set or Reset Macro-Cell 7.3.3.5 3-Bit LUT or Pipe Delay Macro-cell 7.3.3.6 4-Bit LUT or 8-Bit Counter or Delay Macro-Cell 7.3.4 8-Bit Counters and Delay Generators (CNT/DLY) 7.3.4.1 Delay Mode 7.3.4.2 Edge Detector Mode 7.3.4.3 Reset Counter Mode 7.3.5 Programmable Deglitch Filter or Edge Detector Macro-cell 7.3.6 Selectable Frequency Oscillator 7.3.7 Analog Comparators (ACMP) 7.3.8 Voltage Reference (VREF) 7.4 Device Functional Modes 7.4.1 Power-On Reset 8 Application and Implementation 8.1 Application Information 8.2 Typical Application 8.2.1 Design Requirements 8.2.1.1 Power Considerations 8.2.1.2 Input Considerations 8.2.1.3 Output Considerations 8.2.2 Detailed Design Procedure 8.2.3 Application Curves 8.3 Power Supply Recommendations 8.4 Layout 8.4.1 Layout Guidelines 8.4.2 Layout Example 9 Device and Documentation Support 9.1 Receiving Notification of Documentation Updates 9.2 Support Resources 9.3 Trademarks 9.4 Electrostatic Discharge Caution 9.5 Glossary 10 Revision History 11 Mechanical, Packaging, and Orderable Information 11.1 Packaging Option Addendum 11.2 Tape and Reel Information 11.3 Mechanical Data