Datasheet AT89S53 (Microchip) - 9

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AT89S53 Data Memory - RAM Table 7.
Watchdog Timer Period Selection The AT89S53 implements 256 bytes of RAM. The upper 1 0 1 512 ms 128 bytes of RAM occupy a parallel space to the Special 1 1 0 1024 ms Function Registers. That means the upper 128 bytes have the same addresses as the SFR space but are physically 1 1 1 2048 ms separate from SFR space. When an instruction accesses an internal location above
Timer 0 and 1
address 7FH, the address mode used in the instruction Timer 0 and Timer 1 in the AT89S53 operate the same way specifies whether the CPU accesses the upper 128 bytes as Timer 0 and Timer 1 in the AT89C51, AT89C52 and of RAM or the SFR space. Instructions that use direct AT89C55. For further information, see the October 1995 addressing access SFR space. Microcontroller Data Book, page 2-45, section titled, For example, the following direct addressing instruction “Timer/Counters.” accesses the SFR at location 0A0H (which is P2). MOV 0A0H, #data Instructions that use indirect addressing access the upper
Timer 2
128 bytes of RAM. For example, the following indirect Timer 2 is a 16-bit Timer/Counter that can operate as either addressing instruction, where R0 contains 0A0H, accesses a timer or an event counter. The type of operation is the data byte at address 0A0H, rather than P2 (whose selected by bit C/T2 in the SFR T2CON (shown in Table 2). address is 0A0H). Timer 2 has three operating modes: capture, auto-reload MOV @R0, #data (up or down counting), and baud rate generator. The Note that stack operations are examples of indirect modes are selected by bits in T2CON, as shown in Table 8. addressing, so the upper 128 bytes of data RAM are avail- Timer 2 consists of two 8-bit registers, TH2 and TL2. In the able as stack space. Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscil-
Programmable Watchdog Timer
lator periods, the count rate is 1/12 of the oscillator frequency. The programmable Watchdog Timer (WDT) operates from In the Counter function, the register is incremented in an independent oscillator. The prescaler bits, PS0, PS1 response to a 1-to-0 transition at its corresponding external and PS2 in SFR WCON are used to set the period of the input pin, T2. In this function, the external input is sampled Watchdog Timer from 16 ms to 2048 ms. The available during S5P2 of every machine cycle. When the samples timer periods are shown in the following table and the show a high in one cycle and a low in the next cycle, the actual timer periods (at V = 5V) are within ±30% of the CC count is incremented. The new count value appears in the nominal. register during S3P1 of the cycle following the one in which The WDT is disabled by Power-on Reset and during the transition was detected. Since two machine cycles (24 Power-down. It is enabled by setting the WDTEN bit in SFR oscillator periods) are required to recognize a 1-to-0 transi- WCON (address = 96H). The WDT is reset by setting the tion, the maximum count rate is 1/24 of the oscillator WDTRST bit in WCON. When the WDT times out without frequency. To ensure that a given level is sampled at least being reset or disabled, an internal RST pulse is generated once before it changes, the level should be held for at least to reset the CPU. one full machine cycle.
Table 7.
Watchdog Timer Period Selection
Table 8.
Timer 2 Operating Modes
WDT Prescaler Bits RCLK + TCLK CP/RL2 TR2 MODE PS2 PS1 PS0 Period (nominal)
0 0 1 16-bit Auto-Reload 0 0 0 16 ms 0 1 1 16-bit Capture 0 0 1 32 ms 1 X 1 Baud Rate Generator 0 1 0 64 ms X X 0 (Off) 0 1 1 128 ms 1 0 0 256 ms
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0787E–MICRO–3/06 Document Outline Block Diagram Instruction Set Features Description Pin Description VCC GND Port 0 Port 1 Pin Description Port 2 Port 3 RST ALE/PROG PSEN EA/VPP XTAL1 XTAL2 Special Function Registers Data Memory - RAM Programmable Watchdog Timer Timer 0 and 1 Timer 2 Capture Mode Auto-reload (Up or Down Counter) Baud Rate Generator Programmable Clock Out UART Serial Peripheral Interface Interrupts Oscillator Characteristics Idle Mode Status of External Pins During Idle and Power-down Modes Power-down Mode Program Memory Lock Bits Lock Bit Protection Modes(1)(2) Programming the Flash Programming Interface Serial Downloading Either an external system clock is supplied at pin XTAL1 or a crystal needs to be connected across pins XTAL1 and XTAL2. The max... Serial Programming Algorithm Serial Programming Instruction Flash Parallel Programming Modes Flash Programming and Verification Characteristics - Parallel Mode Flash Programming and Verification Waveforms - Parallel Mode Serial Downloading Waveforms Absolute Maximum Ratings* DC Characteristics AC Characteristics External Program and Data Memory Characteristics External Program Memory Read Cycle External Data Memory Read Cycle External Data Memory Write Cycle External Clock Drive Waveforms External Clock Drive Serial Port Timing: Shift Register Mode Test Conditions Shift Register Mode Timing Waveforms AC Testing Input/Output Waveforms(1) Float Waveforms(1) Ordering Information Pin Configurations