Datasheet MAX1951, MAX1952 (Analog Devices) - 10

1MHz, All-Ceramic, 2.6V to 5.5V Input, 2A PWM Step-Down DC-to-DC Regulators
Typical Operating Characteristics), the controller pole. C2 and R1 set a compensation zero. Calculate the responds by regulating the output voltage back to its dominant pole frequency as: nominal state. The controller response time depends on fpEA = 1/(2πx CC x ROEA) the closed-loop bandwidth. A higher bandwidth yields a faster response time, thus preventing the output from Determine the compensation zero frequency is: deviating further from its regulating value. fzEA = 1/(2π x CC x RC)
Compensation Design
For best stability and response performance, set the The double pole formed by the inductor and output closed-loop unity-gain frequency much higher than the capacitor of most voltage-mode controllers introduces a modulator pole frequency. In addition, set the closed- large phase shift, that requires an elaborate compensa- loop crossover unity-gain frequency less than, or equal tion network to stabilize the control loop. The MAX1951/ to, 1/5 of the switching frequency. However, set the MAX1952 utilize a current-mode control scheme that reg- maximum zero crossing frequency to less than 1/3 of ulates the output voltage by forcing the required current the zero frequency set by the output capacitance and through the external inductor, eliminating the double pole its ESR when using POSCAP, SPCAP, OSCON, or other caused by the inductor and output capacitor, and greatly electrolytic capacitors.The loop-gain equation at the simplifying the compensation network. A simple type 1 unity-gain frequency is: compensation with single compensation resistor (R1) and GEA(fc) x GMOD(fc) x VFB/VOUT = 1
MAX1951/MAX1952
compensation capacitor (C2) creates a stable and high- where GEA(fc) = gmEA x R1, and GMOD(fc) = gmc x bandwidth loop. RLOAD x fpMOD/fC, where gmEA = 60µS. An internal transconductance error amplifier compen- R1 calculated as: sates the control loop. Connect a series resistor and capacitor between COMP (the output of the error ampli- R1 = VOUT x K/(gmEA x VFB x GMOD(fc)) fier) and GND to form a pole-zero pair. The external where K is the correction factor due to the extra phase inductor, internal current-sensing circuitry, output introduced by the current loop at high frequencies capacitor, and the external compensation circuit deter- (>100kHz). K is related to the value of the output mine the loop system stability. Choose the inductor and capacitance (see Table 1 for values of K vs. C). Set the output capacitor based on performance, size, and cost. error-amplifier compensation zero formed by R1 and C2 Additionally, select the compensation resistor and at the modulator pole frequency at maximum load. C2 capacitor to optimize control-loop stability. The compo- is calculated as follows: nent values shown in the typical application circuit C2 = (VOUT x COUT/(R1 x IOUT(MAX)) (Figure 2) yield stable operation over a broad range of input-to-output voltages. As the load current decreases, the modulator pole also decreases; however, the modulator gain increases The basic regulator loop consists of a power modulator, accordingly, resulting in a constant closed-loop unity- an output feedback divider, and an error amplifier. The gain frequency. Use the following numerical example to power modulator has DC gain set by gmc x RLOAD, calculate R1 and C2 values of the typical application with a pole-zero pair set by RLOAD, the output capaci- circuit of Figure 2a. tor (COUT), and its ESR. The following equations define the power modulator:
Table 1. K Value
Modulator gain:
DESCRIPTION
GMOD = ΔVOUT/ΔVCOMP = gmc x RLOAD COUT (µF) K V al ues ar e for outp ut i nd uctance fr om 1.2µH Modulator pole frequency: 10 0.55 to 2.2µH . D o not use outp ut i nd uctor s l ar g er fpMOD = 1 / (2 x π x COUT x (RLOAD+ESR)) 22 0.47 than 2.2µH . U se fC = 200kH z to cal cul ate R1 . Modulator zero frequency: fzESR = 1 /(2 x π x COUT x ESR) VOUT = 1.5V where, RLOAD = VOUT/IOUT(MAX), and gmc = 4.2S. IOUT(MAX) = 1.5A The feedback divider has a gain of GFB = VFB / VOUT, C where V OUT = 10µF FB is equal to 0.8V. The transconductance error amplifier has a DC gain, GEA(DC), of 70dB. The com- RESR = 0.010Ω pensation capacitor, C2, and the output resistance of gmEA = 60µS the error amplifier, ROEA (20MΩ), set the dominant
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