Datasheet MAX1951 (Analog Devices) - 9

FabricanteAnalog Devices
Descripción1MHz, All-Ceramic, 2.6V to 5.5V Input, 2A PWM Step-Down DC-to-DC Regulators
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1MHz, All-Ceramic, 2.6V to 5.5V Input,. 2A PWM Step-Down DC-to-DC Regulators. MAX1951/MAX1952. Design Procedure

1MHz, All-Ceramic, 2.6V to 5.5V Input, 2A PWM Step-Down DC-to-DC Regulators MAX1951/MAX1952 Design Procedure

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1MHz, All-Ceramic, 2.6V to 5.5V Input, 2A PWM Step-Down DC-to-DC Regulators MAX1951/MAX1952 Design Procedure
For duty ratios less than 0.5, the input capacitor RMS current is higher than the calculated current. Therefore,
Output Voltage Selection: Adjustable
use a +20% margin when calculating the RMS current
(MAX1951) or Preset (MAX1952)
at lower duty cycles. Use ceramic capacitors for their The MAX1951 provides an adjustable output voltage low ESR, equivalent series inductance (ESL), and lower between 0.8V and VIN. Connect FB to output for 0.8V cost. Choose a capacitor that exhibits less than 10°C output. To set the output voltage of the MAX1951 to a temperature rise at the maximum operating RMS cur- voltage greater than VFB (0.8V typ), connect the output rent for optimum long-term reliability. to FB and GND using a resistive divider, as shown in After determining the input capacitor, check the input Figure 2a. Choose R2 between 2kΩ and 20kΩ, and set ripple voltage due to capacitor discharge when the R3 according to the following equation: high-side MOSFET turns on. Calculate the input ripple R3 = R2 x [(VOUT/VFB) – 1] voltage as follows: The MAX1951 PWM circuitry is capable of a stable min- VIN_RIPPLE = (IOUT x VOUT)/(fSW x VIN x CIN) imum duty cycle of 18%. This limits the minimum output Keep the input ripple voltage less than 3% of the input voltage that can be generated to 0.18 ✕ VIN. Instability voltage. may result for VIN/VOUT ratios below 0.18. The MAX1952 provides a preset output voltage.
Output Capacitor Design
Connect the output to FB, as shown in Figure 2b. The key selection parameters for the output capacitor are capacitance, ESR, ESL, and the voltage rating
Output Inductor Design
requirements. These affect the overall stability, output Use a 2µH inductor with a minimum 2A-rated DC cur- ripple voltage, and transient response of the DC-to-DC rent for most applications. For best efficiency, use an converter. The output ripple occurs due to variations in inductor with a DC resistance of less than 20mΩ and a the charge stored in the output capacitor, the voltage saturation current greater than 3A (min). See Table 2 drop due to the capacitor’s ESR, and the voltage drop for recommended inductors and manufacturers. For due to the capacitor’s ESL. Calculate the output voltage most designs, derive a reasonable inductor value ripple due to the output capacitance, ESR, and ESL as: (LINIT) from the following equation: VRIPPLE = VRIPPLE(C) + VRIPPLE(ESR) + VRIPPLE(ESL) LINIT = VOUT x (VIN - VOUT)/(VIN x LIR x IOUT(MAX) x fSW) where the output ripple due to output capacitance, where fSW is the switching frequency (1MHz typ) of the ESR, and ESL is: oscillator. Keep the inductor current ripple percentage VRIPPLE(C) = IP-P/(8 x COUT x fSW) LIR between 20% and 40% of the maximum load cur- rent for the best compromise of cost, size, and perfor- VRIPPLE(ESR) = IP-P x ESR mance. Calculate the maximum inductor current as: VRIPPLE(ESL) = (IP-P/tON) x ESL or (IP-P/tOFF) x ESL, I whichever is greater L(MAX) = (1 + LIR/2) x IOUT(MAX) Check the final values of the inductor with the output and IP-P the peak-to-peak inductor current is: ripple voltage requirement. The output ripple voltage is IP-P = [ (VIN - VOUT )/fSW x L) ] x VOUT/VIN given by: Use these equations for initial capacitor selection, but VRIPPLE = VOUT x (VIN - VOUT) x ESR / (VIN x LFINAL x fSW) determine final values by testing a prototype or evalua- where ESR is the equivalent series resistance of the tion circuit. As a rule, a smaller ripple current results in output capacitors. less output voltage ripple. Since the inductor ripple current is a factor of the inductor value, the output
Input Capacitor Design
voltage ripple decreases with larger inductance. Use The input filter capacitor reduces peak currents drawn ceramic capacitors for their low ESR and ESL at the from the power source and reduces noise and voltage switching frequency of the converter. The low ESL of ripple on the input caused by the circuit’s switching. ceramic capacitors makes ripple voltages negligible. The input capacitor must meet the ripple current Load transient response depends on the selected requirement (IRMS) imposed by the switching currents output capacitor. During a load transient, the output defined by the following equation: instantly changes by ESR x ILOAD. Before the controller can respond, the output deviates further, depending on I = (1/ V ) × I ( 2 × V × V ( − V )) the inductor and output capacitor values. After a short RMS IN OUT OUT IN OUT time (see the Load Transient Response graph in the
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