Datasheet MAX6701, MAX6701A, MAX6702, MAX6702A, MAX6703, MAX6703A, MAX6704, MAX6705, MAX6705A, MAX6706, MAX6706A, MAX6707, MAX6707A, MAX6708 (Analog Devices) - 6

MAX6701-08/ Low-Voltage, SOT23 µP Supervisors with Power-Fail MAX6701A-03A/ In/Out, Manual Reset, and Watchdog Timer MAX6705A-07A
Pin Description (continued) PIN MAX6701(A) MAX6705(A) NAME FUNCTION MAX6702(A) MAX6704 MAX6706(A) MAX6708 MAX6703(A) MAX6707(A)
Active-Low Watchdog Output (Open Drain or Push- Pull). WDO is asserted whenever the watchdog times out and VCC or the reset inputs are below their respective thresholds. WDO deasserts after a valid WDI transition without a reset timeout period. In the A 8 — 8 — WDO versions, WDO deasserts without a timeout delay when VCC, RST_IN1, and RST_IN2 rises above its threshold. Pull MR low to assert WDO (MAX6701/MAX6702/ MAX6703/MAX6705/MAX6706/MAX6707 only). Pull MR low to deassert WDO (MAX6701(A)/MAX6702(A) / MAX6703(A)/ MAX6705(A)/MAX6706(A)MAX6707(A) only) Active-High Reset Output (Push-Pull). RESET changes from low to high when the VCC input drops below the selected reset threshold (or RST_IN1/RST_IN2 for 7* 8 7* 8 RESET MAX6701(A)/MAX6702(A)/ MAX6703(A), MR is pulled low, or the watchdog triggers a reset (MAX6704 only). RESET remains high for the reset timeout period after the reset conditions are terminated. Input for User-Adjustable VCC2 Monitor. High- impedance input for second internal reset comparator. Connect this pin to an external resistive-divider network 4 — — — RST_IN1 to set the reset threshold voltage; 0.62V (typ) threshold. Connect to VCC when not used. Reset is asserted when either VCC, RST_IN1, or RST_IN2 are below threshold. Input for User-Adjustable VCC3 Monitor. High- impedance input for third internal reset comparator. Connect this pin to an external resistive-divider network 5 — — — RST_IN2 to set the reset threshold voltage; 0.62V (typ) threshold. Connect to VCC when not used. Reset is asserted when either VCC, RST_IN1, or RST_IN2 are below threshold. *RESET active-high for the MAX6702(A)/MAX6706(A).
Detailed Description
RESET stays low. After VCC, RST_IN1, or RST_IN2 rise Figures 1, 2, and 3 are functional diagrams for the above the reset threshold, an internal timer holds RESET MAX6705(A)/MAX6706(A)/MAX6707(A), MAX6704/ low for about 200ms. RESET pulses low whenever MAX6708, and MAX6701(A)/MAX6702(A)/MAX6703(A), VCC dips below the reset threshold, including brownout respectively. conditions. If a brownout occurs in the middle of a previously initiated reset pulse, the pulse continues for
Reset Output
at least another 140ms. On power-down, once VCC A microprocessor’s (µP’s) reset input starts the µP in a falls below the reset threshold, RESET stays low and is known state. The MAX6701–MAX6708 assert reset guaranteed to be 0.4V or less, until VCC drops below 1V. during power-up and prevent code execution errors The MAX6702(A)/MAX6704/MAX6706(A)/MAX6708 during power-down or brownout conditions. active-high RESET output is the complement of the On power-up, once VCC reaches 1V, RESET is a RESET output, and is guaranteed to be valid with VCC guaranteed logic-low of 0.4V or less. As VCC rises, down to 1V. www.maximintegrated.com Maxim Integrated │ 6