Datasheet TLV9101, TLV9102, TLV9104 (Texas Instruments) - 7
| Fabricante | Texas Instruments |
| Descripción | 16-V, 1-MHz, Rail-to-Rail Input/Output, Low Power Op Amp |
| Páginas / Página | 84 / 7 — TLV9101,. TLV9102, TL. V9104. www.ti.com. Figure 5-8. TLV9104 D and PW … |
| Formato / tamaño de archivo | PDF / 6.9 Mb |
| Idioma del documento | Inglés |
TLV9101,. TLV9102, TL. V9104. www.ti.com. Figure 5-8. TLV9104 D and PW Package. 14-Pin SOIC and TSSOP. Top View
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TLV9101, TLV9102, TL V9104 www.ti.com
SBOS943E – FEBRUARY 2019 – REVISED AUGUST 2021 1 4 T T 1± U U 4± OUT1 1 14 OUT4 IN O O IN IN1 2 ± 13 IN4± IN1+ 3 12 IN4+ 6 5 4 3 1 1 1 1 V+ 4 11 V± IN1+ 1 12 IN4+ IN2+ 5 10 IN3+ V+ 2 11 V± Thermal IN2 6 ± 9 IN3± IN2+ 3 Pad 10 IN3+ OUT2 7 8 OUT3 IN2 4 ± 9 IN3± 5 6 7 8 Not to scale
Figure 5-8. TLV9104 D and PW Package
2 3
14-Pin SOIC and TSSOP
C C T N N T U U Not to scale
Top View
O O A. Connect thermal pad to V–. See Section 7.3.9 for more information.
Figure 5-9. TLV9104 RTE Package(A) 16-Pin WQFN With Exposed Thermal Pad Top View
1 4 T T U U O O IN1 1 ± 12 IN4± 4 3 1 1 IN1+ 2 11 IN4+ V+ 3 10 V± IN2+ 4 9 IN3+ 6 7 IN2 5 ± 8 IN3± 2 3 T T Not to scale U U O O
Figure 5-10. TLV9104 RUC Package 14-Pin WQFN With Exposed Thermal Pad Top View Table 5-5. Pin Functions: TLV9104 PIN I/O DESCRIPTION SOIC and NAME WQFN X2QFN TSSOP
IN1+ 3 1 2 I Noninverting input, channel 1 IN1– 2 16 1 I Inverting input, channel 1 IN2+ 5 3 4 I Noninverting input, channel 2 IN2– 6 4 5 I Inverting input, channel 2 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TLV9101 TLV9102 TLV9104 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information for Single Channel 6.5 Thermal Information for Dual Channel 6.6 Thermal Information for Quad Channel 6.7 Electrical Characteristics 6.8 Typical Characteristics 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 EMI Rejection 7.3.2 Phase Reversal Protection 7.3.3 Thermal Protection 7.3.4 Capacitive Load and Stability 7.3.5 Common-Mode Voltage Range 7.3.6 Electrical Overstress 7.3.7 Overload Recovery 7.3.8 Typical Specifications and Distributions 7.3.9 Packages With an Exposed Thermal Pad 7.3.10 Shutdown 7.4 Device Functional Modes 8 Application and Implementation 8.1 Application Information 8.2 Typical Applications 8.2.1 High Voltage Precision Comparator 8.2.1.1 Design Requirements 8.2.1.2 Detailed Design Procedure 8.2.1.3 Application Curve 9 Power Supply Recommendations 10 Layout 10.1 Layout Guidelines 10.2 Layout Example 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support 11.1.1.1 TINA-TI™ (Free Software Download) 11.2 Documentation Support 11.2.1 Related Documentation 11.3 Receiving Notification of Documentation Updates 11.4 Support Resources 11.5 Trademarks 11.6 Electrostatic Discharge Caution 11.7 Glossary 12 Mechanical, Packaging, and Orderable Information
TLV9101, TLV9102, TL V9104 www.ti.com
SBOS943E – FEBRUARY 2019 – REVISED AUGUST 2021 1 4 T T 1± U U 4± OUT1 1 14 OUT4 IN O O IN IN1 2 ± 13 IN4± IN1+ 3 12 IN4+ 6 5 4 3 1 1 1 1 V+ 4 11 V± IN1+ 1 12 IN4+ IN2+ 5 10 IN3+ V+ 2 11 V± Thermal IN2 6 ± 9 IN3± IN2+ 3 Pad 10 IN3+ OUT2 7 8 OUT3 IN2 4 ± 9 IN3± 5 6 7 8 Not to scale
Figure 5-8. TLV9104 D and PW Package
2 3
14-Pin SOIC and TSSOP
C C T N N T U U Not to scale
Top View
O O A. Connect thermal pad to V–. See Section 7.3.9 for more information.
Figure 5-9. TLV9104 RTE Package(A) 16-Pin WQFN With Exposed Thermal Pad Top View
1 4 T T U U O O IN1 1 ± 12 IN4± 4 3 1 1 IN1+ 2 11 IN4+ V+ 3 10 V± IN2+ 4 9 IN3+ 6 7 IN2 5 ± 8 IN3± 2 3 T T Not to scale U U O O
Figure 5-10. TLV9104 RUC Package 14-Pin WQFN With Exposed Thermal Pad Top View Table 5-5. Pin Functions: TLV9104 PIN I/O DESCRIPTION SOIC and NAME WQFN X2QFN TSSOP
IN1+ 3 1 2 I Noninverting input, channel 1 IN1– 2 16 1 I Inverting input, channel 1 IN2+ 5 3 4 I Noninverting input, channel 2 IN2– 6 4 5 I Inverting input, channel 2 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TLV9101 TLV9102 TLV9104 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information for Single Channel 6.5 Thermal Information for Dual Channel 6.6 Thermal Information for Quad Channel 6.7 Electrical Characteristics 6.8 Typical Characteristics 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 EMI Rejection 7.3.2 Phase Reversal Protection 7.3.3 Thermal Protection 7.3.4 Capacitive Load and Stability 7.3.5 Common-Mode Voltage Range 7.3.6 Electrical Overstress 7.3.7 Overload Recovery 7.3.8 Typical Specifications and Distributions 7.3.9 Packages With an Exposed Thermal Pad 7.3.10 Shutdown 7.4 Device Functional Modes 8 Application and Implementation 8.1 Application Information 8.2 Typical Applications 8.2.1 High Voltage Precision Comparator 8.2.1.1 Design Requirements 8.2.1.2 Detailed Design Procedure 8.2.1.3 Application Curve 9 Power Supply Recommendations 10 Layout 10.1 Layout Guidelines 10.2 Layout Example 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support 11.1.1.1 TINA-TI™ (Free Software Download) 11.2 Documentation Support 11.2.1 Related Documentation 11.3 Receiving Notification of Documentation Updates 11.4 Support Resources 11.5 Trademarks 11.6 Electrostatic Discharge Caution 11.7 Glossary 12 Mechanical, Packaging, and Orderable Information