Datasheet TLV9101, TLV9102, TLV9104 (Texas Instruments) - 6
| Fabricante | Texas Instruments |
| Descripción | 16-V, 1-MHz, Rail-to-Rail Input/Output, Low Power Op Amp |
| Páginas / Página | 84 / 6 — TLV9101, TL. V9102,. TLV9104. www.ti.com. Figure 5-6. TLV9102S DGS … |
| Formato / tamaño de archivo | PDF / 6.9 Mb |
| Idioma del documento | Inglés |
TLV9101, TL. V9102,. TLV9104. www.ti.com. Figure 5-6. TLV9102S DGS Package. 10-Pin VSSOP. Top View. Figure 5-7. TLV9102S RUG Package
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TLV9101, TL V9102, TLV9104
SBOS943E – FEBRUARY 2019 – REVISED AUGUST 2021
www.ti.com
IN1+ OUT1 1 10 V+ V– 1 9 IN1– IN1– 2 9 OUT2 10 IN1+ 3 8 IN2– SHDN1 2 8 OUT1 V– 4 7 IN2+ SHDN1 5 6 SHDN2 SHDN2 3 7 V+ Not to scale 5
Figure 5-6. TLV9102S DGS Package
IN2+ 4 6 OUT2
10-Pin VSSOP Top View
Not to scale IN2–
Figure 5-7. TLV9102S RUG Package 10-Pin X2QFN Top View Table 5-4. Pin Functions: TLV9102S PIN I/O DESCRIPTION NAME VSSOP X2QFN
IN1+ 3 10 I Noninverting input, channel 1 IN1– 2 9 I Inverting input, channel 1 IN2+ 7 4 I Noninverting input, channel 2 IN2– 8 5 I Inverting input, channel 2 OUT1 1 8 O Output, channel 1 OUT2 9 6 O Output, channel 2 Shutdown, channel 1: low = amplifier enabled, high = amplifier SHDN1 5 2 I disabled. See Section 7.3.10 for more information. Shutdown, channel 2: low = amplifier enabled, high = amplifier SHDN2 6 3 I disabled. See Section 7.3.10 for more information. V+ 10 7 — Positive (highest) power supply V– 4 1 — Negative (lowest) power supply 6 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9101 TLV9102 TLV9104 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information for Single Channel 6.5 Thermal Information for Dual Channel 6.6 Thermal Information for Quad Channel 6.7 Electrical Characteristics 6.8 Typical Characteristics 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 EMI Rejection 7.3.2 Phase Reversal Protection 7.3.3 Thermal Protection 7.3.4 Capacitive Load and Stability 7.3.5 Common-Mode Voltage Range 7.3.6 Electrical Overstress 7.3.7 Overload Recovery 7.3.8 Typical Specifications and Distributions 7.3.9 Packages With an Exposed Thermal Pad 7.3.10 Shutdown 7.4 Device Functional Modes 8 Application and Implementation 8.1 Application Information 8.2 Typical Applications 8.2.1 High Voltage Precision Comparator 8.2.1.1 Design Requirements 8.2.1.2 Detailed Design Procedure 8.2.1.3 Application Curve 9 Power Supply Recommendations 10 Layout 10.1 Layout Guidelines 10.2 Layout Example 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support 11.1.1.1 TINA-TI™ (Free Software Download) 11.2 Documentation Support 11.2.1 Related Documentation 11.3 Receiving Notification of Documentation Updates 11.4 Support Resources 11.5 Trademarks 11.6 Electrostatic Discharge Caution 11.7 Glossary 12 Mechanical, Packaging, and Orderable Information
TLV9101, TL V9102, TLV9104
SBOS943E – FEBRUARY 2019 – REVISED AUGUST 2021
www.ti.com
IN1+ OUT1 1 10 V+ V– 1 9 IN1– IN1– 2 9 OUT2 10 IN1+ 3 8 IN2– SHDN1 2 8 OUT1 V– 4 7 IN2+ SHDN1 5 6 SHDN2 SHDN2 3 7 V+ Not to scale 5
Figure 5-6. TLV9102S DGS Package
IN2+ 4 6 OUT2
10-Pin VSSOP Top View
Not to scale IN2–
Figure 5-7. TLV9102S RUG Package 10-Pin X2QFN Top View Table 5-4. Pin Functions: TLV9102S PIN I/O DESCRIPTION NAME VSSOP X2QFN
IN1+ 3 10 I Noninverting input, channel 1 IN1– 2 9 I Inverting input, channel 1 IN2+ 7 4 I Noninverting input, channel 2 IN2– 8 5 I Inverting input, channel 2 OUT1 1 8 O Output, channel 1 OUT2 9 6 O Output, channel 2 Shutdown, channel 1: low = amplifier enabled, high = amplifier SHDN1 5 2 I disabled. See Section 7.3.10 for more information. Shutdown, channel 2: low = amplifier enabled, high = amplifier SHDN2 6 3 I disabled. See Section 7.3.10 for more information. V+ 10 7 — Positive (highest) power supply V– 4 1 — Negative (lowest) power supply 6 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9101 TLV9102 TLV9104 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information for Single Channel 6.5 Thermal Information for Dual Channel 6.6 Thermal Information for Quad Channel 6.7 Electrical Characteristics 6.8 Typical Characteristics 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 EMI Rejection 7.3.2 Phase Reversal Protection 7.3.3 Thermal Protection 7.3.4 Capacitive Load and Stability 7.3.5 Common-Mode Voltage Range 7.3.6 Electrical Overstress 7.3.7 Overload Recovery 7.3.8 Typical Specifications and Distributions 7.3.9 Packages With an Exposed Thermal Pad 7.3.10 Shutdown 7.4 Device Functional Modes 8 Application and Implementation 8.1 Application Information 8.2 Typical Applications 8.2.1 High Voltage Precision Comparator 8.2.1.1 Design Requirements 8.2.1.2 Detailed Design Procedure 8.2.1.3 Application Curve 9 Power Supply Recommendations 10 Layout 10.1 Layout Guidelines 10.2 Layout Example 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support 11.1.1.1 TINA-TI™ (Free Software Download) 11.2 Documentation Support 11.2.1 Related Documentation 11.3 Receiving Notification of Documentation Updates 11.4 Support Resources 11.5 Trademarks 11.6 Electrostatic Discharge Caution 11.7 Glossary 12 Mechanical, Packaging, and Orderable Information