Datasheet L99H92 (STMicroelectronics) - 10

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L99H92 Gate drivers Device in active mode with INPMODE=0 (FULL-BRIDGE MODE) Inputs Outputs (in case of no faults) OUTE FWS FSINB DIR PWM AFWE bit HS1 LS1 HS2 LS2 bit bit pin pin pin
1 1 0 1 x 0 OFF ON OFF ON 1 1 1 1 x 0 ON OFF ON OFF 1 0 0 1 1 0 OFF ON OFF OFF 1 x x 1 1 1 OFF ON ON OFF 1 0 1 1 1 0 OFF OFF ON OFF 1. In this case, when the FSINB input pin goes from high to low, the device moves from active mode to fail-safe mode. In fail- safe mode the OUTE control bit is automatically reset and all the gate drivers are forced in sink switch mode so that all the MOSFETs are actively switched off with the maximum available discharge current. 2. In this case, the MOSFET is passively switched off through the internal resistive connection between gate and related source. In all the other cases where the MOSFET is off, it is actively switched off and forced off by the gate driver working in sink switch mode. • If INPMODE = 1, the device works in dual half-bridge mode. The two half-bridges can be driven separately by IN1 and IN2 input pins and can be individually disabled through DIS1 and DIS2 control bits.
Table 3. Dual half-bridge mode Device in active mode with INPMODE=1 (DUAL HALF-BRIDGE MODE) Inputs Outputs (in case of no faults); x=1,2 FSINB OUTE bit DISx bit HSx LSx
1 1 0 Inx Inx 1 0 x OFF(1) OFF(1) All the other cases OFF OFF 1. In this case, the MOSFET is passively switched off through the internal resistive connection between gate and related source. In all the other cases where the MOSFET is off, it is actively switched off and forced off by the gate driver working in sink switch mode. “Inx” means ON if logic level on Inx pin input is high and vice versa.” Inx” means OFF if logic level on Inx pin input is high and vice versa (x=1,2).
2.6.2 Slew rate control (SLEW)
The rising and falling voltage slopes at the outputs can be controlled through slew rate control bits. When the SLEWzx control bits are all set to zero the gate drivers will work in switch mode providing the maximum available current to charge/discharge the MOSFETs input capacitance. The maximum available source/sink current in switch mode is internally limited (IGHx(Ch) and IGLx(Ch)). If any value different from zero is programmed, then the gate drivers will work as current source, instead of low impedance switch, as long as during the MOSFET turning on/off the drain-source voltage over the MOSFETs is above/below the switch threshold (VDSHxfSW and VDSHxrSW). Once the switch threshold is reached, the drivers will work in switch mode. The gate drivers source (charge) and sink (discharge) currents can be independently programmed through dedicated control bits in order to have different output voltage slopes during the turning on and the turning off of the MOSFETs. The MOSFETs gate charging current is programmed using the control bits SLEWCx[4:0], while the MOSFETs gate discharging current is programmed using the control bits SLEWDx[4:0]. The gate current is set depending on the SLEWzx control bits value according to the formula: IGATE = SLEWzx 4:0 31 *IGATEMAX (1) SLEWzx can be either SLEWDx or SLEWCx, while IGATEMAX can be either IGLxymax or IGHxymax (y=r for source current; y=f for sink current). Programming SLEWzx[4:0] to 0 disables the slew rate control and enables gate driving through the low- impedance switch during the entire turning on/off process.
DS14069
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Rev 4 page 10/77
Document Outline L99H92 Features Applications Description 1 Block diagram and pins description 1.1 Block diagram 1.2 Pinout 1.3 Pins description 2 Device description 2.1 Supply pins 2.1.1 VS overvoltage warning (VSOVW) 2.1.2 VDH overvoltage (VDHOV) 2.1.3 VDH undervoltage (VDHUV) 2.1.4 VDD overvoltage (VDDOV) 2.1.5 Digital input/output overvoltage (DIOOV) 2.1.6 Power-on reset (POR) 2.2 Standby mode (EN) 2.3 Active mode (OUTE) 2.4 Thermal warning and thermal shutdown (TW/TSD) 2.5 Charge pump (CPOUT) 2.6 Gate drivers 2.6.1 Outputs driving signals (PWM/IN1 and DIR/IN2) 2.6.2 Slew rate control (SLEW) 2.6.3 Short circuit detection / drain-source monitoring (DSHS/DSLS) 2.6.4 Programmable cross current protection time (DT) 2.7 Diagnostic in off-mode (O1DS/O2DS) 2.8 Fail-safe output switch-off input not pin (FSINB) 2.9 Diagnostic not output (DIAGN) 2.10 Current monitors 2.11 Window watchdog (WDG) 3 Application 4 Serial peripheral interface (SPI) 4.1 ST SPI 4.1 4.1.1 Physical layer 4.1.2 Clock and data characteristics 4.1.3 Communication protocol 4.1.4 Address definition 5 Electrical characteristics 5.1 Absolute maximum ratings 5.2 ESD protection 5.3 Thermal data 5.4 Electrical characteristics 5.4.1 Supply, supply monitoring 5.4.2 Power-on reset 5.5 Charge pump 5.6 Full-bridge driver 5.7 VDS monitoring thresholds 5.7.1 Open-load monitoring external full-bridges 5.8 Current sense amplifiers (CSA) 5.9 Fail-safe switch-off input FSINB 5.10 Enable 5.11 DIAGN 5.12 Watchdog 5.13 SPI electrical characteristics 5.14 Oscillator 5.15 Operating modes 6 SPI registers 6.1 Global status byte GSB 6.2 Register map overview 6.3 Status registers 6.4 Control registers 7 Package information 7.1 QFN32L 5x5 mm package information 7.2 TQFP32L 7x7 mm package information Revision history