Datasheet NCP565, NCV565 (ON Semiconductor) - 8
| Fabricante | ON Semiconductor |
| Descripción | Linear Regulator -Low Dropout 1.5 A |
| Páginas / Página | 17 / 8 — NCP565, NCV565. Figure 19. Schematic for Transient Response Measurement. … |
| Formato / tamaño de archivo | PDF / 428 Kb |
| Idioma del documento | Inglés |
NCP565, NCV565. Figure 19. Schematic for Transient Response Measurement. PCB Layout Considerations. NCP565
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NCP565, NCV565
GEN Vout −VCC NCP565 V RL Vin Evaluation Board Pulse + GND + GND Scope Voltage Probe
Figure 19. Schematic for Transient Response Measurement PCB Layout Considerations
several capacitors in parallel. This reduces the overall ESR Good PCB layout plays an important role in achieving and reduces the instantaneous output voltage drop under good load transient performance. Because it is very sensitive transient load conditions. The output capacitor network to its PCB layout, particular care has to be taken when should be as close as possible to the load for the best results. tackling Printed Circuit Board (PCB) layout. The figures The schematic of NCP565 typical application circuit, which below give an example of a layout where parasitic elements this PCB layout is base on, is shown in Figure 20. The output are minimized. For microprocessor applications it is voltage is set to 3.3 V for this demonstration board according customary to use an output capacitor network consisting of to the feedback resistors in the Table 1. V 2 out V V 4 in in Vout
NCP565
1 C C NC Adj 5 1 2 C4 C3 C3 150 m 150 m GND 10 m 150 m 150 m 3 GND GND R2 R1 15.8 k 42.2 k C6 5.6 p
Figure 20. Schematic of NCP565 Typical Application Circuit www.onsemi.com 8
NCP565, NCV565
GEN Vout −VCC NCP565 V RL Vin Evaluation Board Pulse + GND + GND Scope Voltage Probe
Figure 19. Schematic for Transient Response Measurement PCB Layout Considerations
several capacitors in parallel. This reduces the overall ESR Good PCB layout plays an important role in achieving and reduces the instantaneous output voltage drop under good load transient performance. Because it is very sensitive transient load conditions. The output capacitor network to its PCB layout, particular care has to be taken when should be as close as possible to the load for the best results. tackling Printed Circuit Board (PCB) layout. The figures The schematic of NCP565 typical application circuit, which below give an example of a layout where parasitic elements this PCB layout is base on, is shown in Figure 20. The output are minimized. For microprocessor applications it is voltage is set to 3.3 V for this demonstration board according customary to use an output capacitor network consisting of to the feedback resistors in the Table 1. V 2 out V V 4 in in Vout
NCP565
1 C C NC Adj 5 1 2 C4 C3 C3 150 m 150 m GND 10 m 150 m 150 m 3 GND GND R2 R1 15.8 k 42.2 k C6 5.6 p
Figure 20. Schematic of NCP565 Typical Application Circuit www.onsemi.com 8