Datasheet TMUX4051, TMUX4052, TMUX4053 (Texas Instruments) - 5

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TMUX4051, TMUX4052 , TMUX4053 www.ti.com
SCDS445B – MAY 2022 – REVISED MARCH 2023 S0B 1 16 VDD S0B 1 16 VDD S2B 2 15 S2A S2B 2 15 S2A DB 3 14 S1A DB 3 14 S1A S3B 4 13 DA S3B 4 13 DA S1B 5 12 S0A S1B 5 12 S0A 6 11 S3A 6 11 S3A VSS 7 10 A0 VSS 7 10 A0 GND 8 9 A1 GND 8 9 A1 Not to scale Not to scale
Figure 6-5. TMUX4052 DYY Package, 16-Pin Figure 6-4. TMUX4052 PW Package, 16-Pin TSSOP SOT-23-THIN (Top View) (Top View)
S0B VDD 1 16 S2B 2 15 S2A DB 3 14 S1A Thermal S3B 4 13 DA Pad S1B 5 12 S0A 6 11 S3A VSS 7 10 A0 8 9 Not to scale A1 GND
Figure 6-6. TMUX4052 BQB Package, 16-Pin WQFN (Top View) Table 6-2. Pin Functions TMUX4052 PIN TYPE
(1)
DESCRIPTION
(2)
NAME NO.
S0B 1 I/O Source pin 0 of mux B. Can be an input or output. S2B 2 I/O Source pin 2 of mux B. Can be an input or output. DB 3 I/O Drain pin (common) of mux B. Can be an input or output. S3B 4 I/O Source pin 3 of mux B. Can be an input or output. S1B 5 I/O Source pin 1 of mux B. Can be an input or output. Active low logic enable. When this pin is high, all switches are turned off. When this pin is low, the EN 6 I A[1:0] address inputs determine which switch is turned on. Negative power supply. This pin is the most negative power-supply potential. For reliable operation, VSS 7 P connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND. GND 8 P Ground (0 V) reference A1 9 I Address line 1. Table 9-2 provides information about how A1 controls the switch configuration. A0 10 I Address line 0. Table 9-2 provides information about how A0 controls the switch configuration. S3A 11 I/O Source pin 3 of mux A. Can be an input or output. S0A 12 I/O Source pin 0 of mux A. Can be an input or output. DA 13 I/O Drain pin (common) of mux A. Can be an input or output. S1A 14 I/O Source pin 1 of mux A. Can be an input or output. S2A 15 I/O Source pin 2 of mux A. Can be an input or output. Positive power supply. This pin is the most positive power-supply potential. For reliable operation, VDD 16 P connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND. The thermal pad is not connected internally. It is recommended that the pad be left floating or tied to Thermal pad — GND. (1) I = input, O = output, I/O = input and output, P = power. (2) For what to do with unused pins, refer to Section 9.3.4 . Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TMUX4051 TMUX4052 TMUX4053 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Device Comparison Table 6 Pin Configuration and Functions 7 Specifications 7.1 Absolute Maximum Ratings 7.2 ESD Ratings 7.3 Thermal Information: TMUX405x 7.4 Recommended Operating Conditions 7.5 Electrical Characteristics 7.6 AC Performance Characteristics 7.7 Timing Characteristics 7.8 Typical Characteristics 8 Parameter Measurement Information 8.1 On-Resistance 8.2 Off-Leakage Current 8.3 On-Leakage Current 8.4 Transition Time 8.5 Break-Before-Make 8.6 tON(EN) and tOFF(EN) 8.7 Propagation Delay 8.8 Charge Injection 8.9 Off Isolation 8.10 Crosstalk 8.11 Bandwidth 9 Detailed Description 9.1 Overview 9.2 Functional Block Diagram 9.3 Feature Description 9.3.1 Bidirectional Operation 9.3.2 Rail-to-Rail Operation 9.3.3 1.8 V Logic Compatible Inputs 9.3.4 Device Functional Modes 9.3.5 Truth Tables 10 Application and Implementation 10.1 Application Information 10.2 Typical Application 10.3 Design Requirements 10.4 Detailed Design Procedure 10.5 Application Curves 10.6 Power Supply Recommendations 10.7 Layout 10.7.1 Layout Guidelines 10.7.2 Layout Example 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation 11.2 Receiving Notification of Documentation Updates 11.3 Support Resources 11.4 Trademarks 11.5 Electrostatic Discharge Caution 11.6 Glossary 12 Mechanical, Packaging, and Orderable Information Sheets and Views 4224642(B)-02_PKG_OUTLINE 4224642(B)-03_BOARD_LAYOUT 4224642(B)-04_STENCIL Sheets and Views 4224640-02_PKG_OULINE 4224640-03_BOARD_LAYOUT 4224640-04_STENCIL