Datasheet MC33023, MC34023 (ON Semiconductor) - 10

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MC34023, MC33023 OPERATING DESCRIPTION
The MC33023 and MC34023 series are high speed, fixed output of the error amplifier to less than its normal output frequency, single−ended pulse width modulator controllers voltage, thus limiting the duty cycle. The time it takes for a optimized for high frequency operation. They are capacitor to reach full charge is given by: specifically designed for Off−Line and DC−to−DC converter applications offering the designer a cost effective t [ (4.5 • 105) CSoft-Start solution with minimal external components. A A Soft−Start latch is incorporated to prevent erratic representative block diagram is shown in Figure 19. operation of this circuitry. Two conditions can cause the Soft−Start circuit to latch so that the Soft−Start capacitor
Oscillator
stays discharged. The first condition is activation of an The oscillator frequency is programmed by the values undervoltage lockout of either VCC or Vref. The second selected for the timing components RT and CT. The RT pin condition is when current sense input exceeds 1.4 V. Since is set to a temperature compensated 3.0 V. By selecting the this latch is “set dominant”, it cannot be reset until either of value of RT, the charge current is set through a current mirror these signals is removed and, the voltage at CSoft−Start is less for the timing capacitor CT. This charge current runs than 0.5 V. continuously through CT. The discharge current is ratioed to be 10 times the charge current, which yields the maximum
PWM Comparator and Latch
duty cycle of 90%. CT is charged to 2.8 V and discharged to A PWM circuit typically compares an error voltage with 1.0 V. During the discharge of CT, the oscillator generates an a ramp signal. The outcome of this comparison determines internal blanking pulse that resets the PWM Latch and, the state of the output. In voltage mode operation the ramp inhibits the outputs. The threshold voltage on the oscillator signal is the voltage ramp of the timing capacitor. In current comparator is trimmed to guarantee an oscillator accuracy mode operation the ramp signal is the voltage ramp induced of 5.0% at 25°C. in a current sensing element. The ramp input of the PWM Additional dead time can be added by externally comparator is pinned out so that the user can decide which increasing the charge current to CT as shown in Figure 24. mode of operation best suits the application requirements. This changes the charge to discharge ratio of CT which is set The ramp input has a 1.25 V offset such that whenever the internally to Icharge/10 Icharge. The new charge to discharge voltage at this pin exceeds the error amplifier output voltage ratio will be: minus 1.25 V, the PWM comparator will cause the PWM latch to set, disabling the outputs. Once the PWM latch is set, Iadditional ) Icharge % Deadtime + only a blanking pulse by the oscillator can reset it, thus 10 (Icharge) initiating the next cycle. A bidirectional clock pin is provided for synchronization
Current Limiting and Shutdown
or for master/slave operation. As a master, the clock pin A pin is provided to perform current limiting and provides a positive output pulse during the discharge of CT. shutdown operations. Two comparators are connected to the As a slave, the clock pin is an input that resets the PWM latch input of this pin. The reference voltage for the current limit and blanks the drive output, but does not discharge CT. comparator is not set internally. A pin is provided so the user Therefore, the oscillator is not synchronized by driving the can set the voltage. When the voltage at the current limit clock pin alone. Figures 28, 29 and 30 provide suggested input pin exceeds the externally set voltage, the PWM latch synchronization. is set, disabling the output. In this way cycle−by−cycle
Error Amplifier
current limiting is accomplished. If a current limit resistor is A fully compensated Error Amplifier is provided. It used in series with the power devices, the value of the features a typical DC voltage gain of 95 dB and a gain resistor is found by: bandwidth product of 8.3 MHz with 75 degrees of phase ILimit Reference Voltage margin (Figure 4). Typical application circuits will have the RSense + noninverting input tied to the reference. The inverting input Ipk (switch) will typically be connected to a feedback voltage generated If the voltage at this pin exceeds 1.4 V, the second from the output of the switching power supply. Both inputs comparator is activated. This comparator sets a latch which, have a common mode voltage (VCM) input range of 1.5 V to in turn, causes the soft start capacitor to be discharged. In this 5.5 V. The Error Amplifier Output is provided for external way a “hiccup” mode of recovery is possible in the case of loop compensation. output short circuits. If a current limit resistor is used in series with the output devices, the peak current at which the
Soft−Start Latch
controller will enter a “hiccup” mode is given by: Soft−Start is accomplished in conjunction with an external capacitor. The Soft−Start capacitor is charged by an internal 9.0 mA current source. This capacitor clamps the
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