Datasheet MC74VHC02 (ON Semiconductor) - 2
| Fabricante | ON Semiconductor |
| Descripción | Quad 2-Input NOR Gate |
| Páginas / Página | 6 / 2 — www.onsemi.com. MARKING. DIAGRAMS. Features. SOIC−14. D SUFFIX. CASE … |
| Formato / tamaño de archivo | PDF / 146 Kb |
| Idioma del documento | Inglés |
www.onsemi.com. MARKING. DIAGRAMS. Features. SOIC−14. D SUFFIX. CASE 751A. TSSOP−14. DT SUFFIX. CASE 948G. PIN ASSIGNMENT. FUNCTION TABLE
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MC74VHC02
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link to page 4 MC74VHC02 Quad 2-Input NOR Gate The MC74VHC02 is an advanced high speed CMOS 2−input NOR gate fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The internal circuit is composed of three stages, including a buffer
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output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
MARKING
systems to 3.0 V systems.
DIAGRAMS Features
14 •
SOIC−14
High Speed: t VHC02G PD = 3.6 ns (Typ) at VCC = 5.0 V
D SUFFIX
• AWLYWW Low Power Dissipation: ICC = 2 mA (Max) at TA = 25°C
CASE 751A
• 1 1 High Noise Immunity: VNIH = VNIL = 28% VCC • Power Down Protection Provided on Inputs • Balanced Propagation Delays 14 • Designed for 2.0 V to 5.5 V Operating Range
TSSOP−14
VHC • 02 Low Noise: V
DT SUFFIX
OLP = 0.8 V (Max) ALYW •
CASE 948G
Pin and Function Compatible with Other Standard Logic Families 1 • 1 Latchup Performance Exceeds 300mA • ESD Performance: A = Assembly Location Human Body Model > 2000 V; WL, L = Wafer Lot Machine Model > 200 V Y = Year • Chip Complexity: 40 FETs or 10 Equivalent Gates WW, W = Work Week • G or = Pb−Free Package NLV Prefix for Automotive and Other Applications Requiring (Note: Microdot may be in either location) Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable • These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
PIN ASSIGNMENT
Compliant Y1 1 14 VCC 2 A1 2 13 Y4 A1 1 Y1 3 B1 3 12 B4 B1 Y2 4 11 A4 5 A2 4 A2 5 10 Y3 Y2 6 B2 B2 6 9 B3 Y = A + B 8 GND 7 8 A3 A3 10 Y3 9 B3
FUNCTION TABLE
11 A4
Inputs Output
13 Y4 12
A B Y
B4 L L H
Figure 1. LOGIC DIAGRAM
L H L H L L H H L
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. © Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
December, 2015 − Rev. 6 MC74VHC02/D
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output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
MARKING
systems to 3.0 V systems.
DIAGRAMS Features
14 •
SOIC−14
High Speed: t VHC02G PD = 3.6 ns (Typ) at VCC = 5.0 V
D SUFFIX
• AWLYWW Low Power Dissipation: ICC = 2 mA (Max) at TA = 25°C
CASE 751A
• 1 1 High Noise Immunity: VNIH = VNIL = 28% VCC • Power Down Protection Provided on Inputs • Balanced Propagation Delays 14 • Designed for 2.0 V to 5.5 V Operating Range
TSSOP−14
VHC • 02 Low Noise: V
DT SUFFIX
OLP = 0.8 V (Max) ALYW •
CASE 948G
Pin and Function Compatible with Other Standard Logic Families 1 • 1 Latchup Performance Exceeds 300mA • ESD Performance: A = Assembly Location Human Body Model > 2000 V; WL, L = Wafer Lot Machine Model > 200 V Y = Year • Chip Complexity: 40 FETs or 10 Equivalent Gates WW, W = Work Week • G or = Pb−Free Package NLV Prefix for Automotive and Other Applications Requiring (Note: Microdot may be in either location) Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable • These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
PIN ASSIGNMENT
Compliant Y1 1 14 VCC 2 A1 2 13 Y4 A1 1 Y1 3 B1 3 12 B4 B1 Y2 4 11 A4 5 A2 4 A2 5 10 Y3 Y2 6 B2 B2 6 9 B3 Y = A + B 8 GND 7 8 A3 A3 10 Y3 9 B3
FUNCTION TABLE
11 A4
Inputs Output
13 Y4 12
A B Y
B4 L L H
Figure 1. LOGIC DIAGRAM
L H L H L L H H L
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. © Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
December, 2015 − Rev. 6 MC74VHC02/D