Datasheet EFM8SB2 (Silicon Labs) - 8

EFM8SB2 Data Sheet System Overview
Watchdog Timer (WDT0)
The device includes a programmable watchdog timer (WDT) integrated within the PCA0 peripheral. A WDT overflow forces the MCU into the reset state. To prevent the reset, the WDT must be restarted by application software before overflow. If the system experiences a software or hardware malfunction preventing the software from restarting the WDT, the WDT overflows and causes a reset. Following a reset, the WDT is automatically enabled and running with the default maximum time interval. If needed, the WDT can be disabled by system software. The state of the RSTb pin is unaffected by this reset. The Watchdog Timer integrated in the PCA0 peripheral has the following features: • Programmable timeout interval • Runs from the selected PCA clock source • Automatically enabled after any system reset
3.6 Communications and Other Digital Peripherals Universal Asynchronous Receiver/Transmitter (UART0)
UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates. Received data buffering allows UART0 to start reception of a second incoming data byte before software has finished reading the previous data byte. The UART module provides the following features: • Asynchronous transmissions and receptions. • Baud rates up to SYSCLK/2 (transmit) or SYSCLK/8 (receive). • 8- or 9-bit data. • Automatic start and stop generation. • Single-byte FIFO on transmit and receive.
Serial Peripheral Interface (SPI0 and SPI1)
The serial peripheral interface (SPI) module provides access to a flexible, full-duplex synchronous serial bus. The SPI can operate as a master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input to select the SPI in slave mode, or to disable master mode operation in a multi-master environment, avoiding contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can also be configured as a firmware-controlled chip-select output in master mode, or disabled to reduce the number of pins required. Additional general purpose port I/O pins can be used to select multiple slave devices in master mode. The SPI module includes the following features: • Supports 3- or 4-wire operation in master or slave modes. • Supports external clock frequencies up to SYSCLK / 2 in master mode and SYSCLK / 10 in slave mode. • Support for four clock phase and polarity options. • 8-bit dedicated clock clock rate generator. • Support for multiple masters on the same data lines.
System Management Bus / I2C (SMB0)
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specifica- tion, version 1.1, and compatible with the I2C serial bus. The SMBus module includes the following features: • Standard (up to 100 kbps) and Fast (400 kbps) transfer speeds. • Support for master, slave, and multi-master modes. • Hardware synchronization and arbitration for multi-master mode. • Clock low extending (clock stretching) to interface with faster masters. • Hardware support for 7-bit slave and general call address recognition. • Firmware support for 10-bit slave address decoding. • Ability to inhibit all slave states. • Programmable data setup/hold times.
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| Smart. Connected. Energy-friendly. Rev. 1.2 | 7 Document Outline 1. Feature List 2. Ordering Information 3. System Overview 3.1 Introduction 3.2 Power 3.3 I/O 3.4 Clocking 3.5 Counters/Timers and PWM 3.6 Communications and Other Digital Peripherals 3.7 Analog 3.8 Reset Sources 3.9 Debugging 3.10 Bootloader 4. Electrical Specifications 4.1 Electrical Characteristics 4.1.1 Recommended Operating Conditions 4.1.2 Power Consumption 4.1.3 Reset and Supply Monitor 4.1.4 Flash Memory 4.1.5 Power Management Timing 4.1.6 Internal Oscillators 4.1.7 Crystal Oscillator 4.1.8 External Clock Input 4.1.9 ADC 4.1.10 Voltage References 4.1.11 Temperature Sensor 4.1.12 Comparators 4.1.13 Programmable Current Reference (IREF0) 4.1.14 Port I/O 4.2 Thermal Conditions 4.3 Absolute Maximum Ratings 4.4 Typical Performance Curves 5. Typical Connection Diagrams 5.1 Power 5.2 Debug 5.3 Other Connections 6. Pin Definitions 6.1 EFM8SB2x-QFN32 Pin Definitions 6.2 EFM8SB2x-QFN24 Pin Definitions 6.3 EFM8SB2x-QFP32 Pin Definitions 7. QFN32 Package Specifications 7.1 QFN32 Package Dimensions 7.2 QFN32 PCB Land Pattern 7.3 QFN32 Package Marking 8. QFN24 Package Specifications 8.1 QFN24 Package Dimensions 8.2 QFN24 PCB Land Pattern 8.3 QFN24 Package Marking 9. QFP32 Package Specifications 9.1 QFP32 Package Dimensions 9.2 QFP32 PCB Land Pattern 9.3 QFP32 Package Marking 10. Revision History 10.1 Revision 1.2 10.2 Revision 1.1 Table of Contents