Datasheet EFM8SB2 (Silicon Labs) - 2

EFM8SB2 Data Sheet Feature List
1. Feature List
The EFM8SB2 highlighted features are listed below. • Core: • Timers/Counters and PWM: • Pipelined CIP-51 Core • 32-bit Real Time Clock (RTC) • Fully compatible with standard 8051 instruction set • 6-channel programmable counter array (PCA) supporting • 70% of instructions execute in 1-2 clock cycles PWM, capture/compare, and frequency output modes with • 25 MHz maximum operating frequency watchdog timer function • Memory: • 4 x 16-bit general-purpose timers • Up to 64 kB flash memory, in-system re-programmable • Communications and Digital Peripherals: from firmware. • UART • Up to 4352 bytes RAM (including 256 bytes standard 8051 • 2 x SPI™ Master / Slave RAM and 4096 bytes on-chip XRAM) • SMBus™/I2C™ Master / Slave • Power: • External Memory Interface (EMIF) • Internal LDO regulator for CPU core voltage • 16-bit/32-bit CRC unit, supporting automatic CRC of flash at • Power-on reset circuit and brownout detectors 1024-byte boundaries • I/O: Up to 24 total multifunction I/O pins: • Analog: • All pins 5 V tolerant under bias • Programmable current reference (IREF0) • Flexible peripheral crossbar for peripheral routing • 10-Bit Analog-to-Digital Converter (ADC0) • 5 mA source, 12.5 mA sink allows direct drive of LEDs • 2 x Low-current analog comparators • Clock Sources: • On-Chip, Non-Intrusive Debugging • Internal 20 MHz low power oscillator with ±10% accuracy • Full memory and register inspection • Internal 24.5 MHz precision oscillator with ±2% accuracy • Four hardware breakpoints, single-stepping • External RTC 32 kHz crystal • Pre-loaded UART bootloader • External crystal, RC, C, and CMOS clock options • Temperature range -40 to 85 ºC • Single power supply 1.8 to 3.6 V • QFP32, QFN32, and QFN24 packages With on-chip power-on reset, voltage supply monitor, watchdog timer, and clock oscillator, the EFM8SB2 devices are truly standalone system-on-a-chip solutions. The flash memory is reprogrammable in-circuit, providing non-volatile data storage and allowing field up- grades of the firmware. The on-chip debugging interface (C2) allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production MCU installed in the final application. This debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, and run and halt commands. All analog and digital peripherals are fully functional while debugging. Each device is specified for 1.8 to 3.6 V operation and is available in 24-pin QFN, 32-pin QFN, or 32-pin QFP pack- ages. All package options are lead-free and RoHS compliant.
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| Smart. Connected. Energy-friendly. Rev. 1.2 | 1 Document Outline 1. Feature List 2. Ordering Information 3. System Overview 3.1 Introduction 3.2 Power 3.3 I/O 3.4 Clocking 3.5 Counters/Timers and PWM 3.6 Communications and Other Digital Peripherals 3.7 Analog 3.8 Reset Sources 3.9 Debugging 3.10 Bootloader 4. Electrical Specifications 4.1 Electrical Characteristics 4.1.1 Recommended Operating Conditions 4.1.2 Power Consumption 4.1.3 Reset and Supply Monitor 4.1.4 Flash Memory 4.1.5 Power Management Timing 4.1.6 Internal Oscillators 4.1.7 Crystal Oscillator 4.1.8 External Clock Input 4.1.9 ADC 4.1.10 Voltage References 4.1.11 Temperature Sensor 4.1.12 Comparators 4.1.13 Programmable Current Reference (IREF0) 4.1.14 Port I/O 4.2 Thermal Conditions 4.3 Absolute Maximum Ratings 4.4 Typical Performance Curves 5. Typical Connection Diagrams 5.1 Power 5.2 Debug 5.3 Other Connections 6. Pin Definitions 6.1 EFM8SB2x-QFN32 Pin Definitions 6.2 EFM8SB2x-QFN24 Pin Definitions 6.3 EFM8SB2x-QFP32 Pin Definitions 7. QFN32 Package Specifications 7.1 QFN32 Package Dimensions 7.2 QFN32 PCB Land Pattern 7.3 QFN32 Package Marking 8. QFN24 Package Specifications 8.1 QFN24 Package Dimensions 8.2 QFN24 PCB Land Pattern 8.3 QFN24 Package Marking 9. QFP32 Package Specifications 9.1 QFP32 Package Dimensions 9.2 QFP32 PCB Land Pattern 9.3 QFP32 Package Marking 10. Revision History 10.1 Revision 1.2 10.2 Revision 1.1 Table of Contents