Datasheet AP43776Q (Diodes) - 7
| Fabricante | Diodes |
| Descripción | Automotive-Grade Dual-Channel USB Type-C Protocol Decoder |
| Páginas / Página | 13 / 7 — AP43776Q. Functional Overview. Function Description. USB Type-C CC Logic … |
| Formato / tamaño de archivo | PDF / 973 Kb |
| Idioma del documento | Inglés |
AP43776Q. Functional Overview. Function Description. USB Type-C CC Logic & PD 3.1 Engine
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AP43776Q Functional Overview Function Description
The AP43776Q is a highly integrated, dual-channel, USB Type-C PD3.1/ PPS/ QC5 protocol decoder, and has passed the certification of USB-IF PD3.1/PPS and QualcommTM QC5.0. To ensure two independent PD3.1 PPS protocol decoding operations are in full compliance with critical USB Power Delivery specification rev 3.1, the AP43776Q implements a combination of hardware and MCU firmware to leverage quick response times from the hardware and maintain software flexibility. To reduce noise interference during chip application, I2C communication is used between the PD controller and DC/DC converter.
USB Type-C CC Logic & PD 3.1 Engine
The AP43776Q supports the latest USB Power Delivery Specification Revision 3.1, and is compliant to USB Type-C Cable and Connector Specification Revision 2.1. The device can support the full range of PPS APDO (augmented power data object) from 3.3V to 21V with 20mV/step voltage resolution and up to 6A current with 50mA/step resolution for power management. The device has two independent protocol decoders and plays as two DFPs (providers only). To leverage quick response times from the hardware circuitry, it consists of USB Type-C baseband transceivers, physical-layer logic, and DP/DM transceivers for supporting QC and FCP protocols. All communications are half-duplex, and the Physical Layer provides collision avoidance to minimize communication errors during handshake. These transceivers perform the BMC and the 4b/5b encoding and decoding functions as well as the analog front end. To perform the CC detection logic, the current sources and switches are integrated to perform the RP resistors, as required by USB Type-C specifications to implement connection detection, plug orientation detection, and to establish USB DFP role. Also, it can be programmed to indicate the complete range of current capacity on VBUS. The built-in VCONN power switch is provided to the cable e-Marker over the CC pin that is determined not to be connected to the CC wire as soon as a cable is plugged in. The maximum output power of VCONN is 150mW.
USB BC 1.2 DCP(Dedicated Charging Port) Mode and Quick Charging Legacy
The AP43776Q integrates the USB dedicated charging port auto detect function to recognize most of mainstream portable devices. It supports the following charging schemes like BC1.2 DCP mode, Apple mode, Chinese Telecommunications Industry Standard YD/T 1591-2009, FCP Class A, and Qualcomm Quick Charging HVDCP mode (QC2.0/3.0/4/4+/5).
DisplayPort Alternate Mode Support
The AP43776Q supports DisplayPort Alternate Mode on USB Type-C standard with DP mode Discovery, Enter, Exit included by decoding out the control signals from CC handshaking, and delivering to the mux switches through I2C interface, and then the USB Type-C data stream can be routed to the DP/HDMI receiver correctly. Also, the DP configuration, status update, and source/sink connection detection are provided.
USB BC1.2 CDP Mode
The AP43776Q also supports BC 1.2 CDP (Charging Downstream Port) Mode. It can be enabled by I2C communication. When CDP is enabled, QC/Apple and DCP modes on DP and DM will be turned off.
Bias and Power
The AP43776Q operates from a single external supply source, VCC. VCC is used for analog circuitry and goes through internal regulators to generate all of the voltage and current references for chip operation, without the need for external capacitor decoupling. The AP43776Q has two different power modes: normal and sleep. During normal operation, the AP43771 consumes less than 3mA. During sleep mode, its current can be reduced to around 0.5mA automatically.
I2C Interface
For USB Type-C PD charging system, the I2C interface pins (SCK, SDA) are used to communicate between the PD decoder and DC/DC controller/converter to replace analog signal feedback with much higher noise immunity. The AP43776Q is in charge of the CC1/CC2 or DP/DN protocol handshake with the attached device, and deliver the voltage and current request to DC/DC controller/converter through I2C bus. The AP43776Q, working as an I2C master device, keeps track of charging capability of each USB Type-C port through I2C interface pins at the same time. Based on the user-specified and desired smart power-sharing options for the two charging ports, the AP43776Q decides the final charging profiles for each port. AP43776Q 7 of 13 November 2022 Document number: DS43207 Rev. 2 - 2
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© Diodes Incorporated
The AP43776Q is a highly integrated, dual-channel, USB Type-C PD3.1/ PPS/ QC5 protocol decoder, and has passed the certification of USB-IF PD3.1/PPS and QualcommTM QC5.0. To ensure two independent PD3.1 PPS protocol decoding operations are in full compliance with critical USB Power Delivery specification rev 3.1, the AP43776Q implements a combination of hardware and MCU firmware to leverage quick response times from the hardware and maintain software flexibility. To reduce noise interference during chip application, I2C communication is used between the PD controller and DC/DC converter.
USB Type-C CC Logic & PD 3.1 Engine
The AP43776Q supports the latest USB Power Delivery Specification Revision 3.1, and is compliant to USB Type-C Cable and Connector Specification Revision 2.1. The device can support the full range of PPS APDO (augmented power data object) from 3.3V to 21V with 20mV/step voltage resolution and up to 6A current with 50mA/step resolution for power management. The device has two independent protocol decoders and plays as two DFPs (providers only). To leverage quick response times from the hardware circuitry, it consists of USB Type-C baseband transceivers, physical-layer logic, and DP/DM transceivers for supporting QC and FCP protocols. All communications are half-duplex, and the Physical Layer provides collision avoidance to minimize communication errors during handshake. These transceivers perform the BMC and the 4b/5b encoding and decoding functions as well as the analog front end. To perform the CC detection logic, the current sources and switches are integrated to perform the RP resistors, as required by USB Type-C specifications to implement connection detection, plug orientation detection, and to establish USB DFP role. Also, it can be programmed to indicate the complete range of current capacity on VBUS. The built-in VCONN power switch is provided to the cable e-Marker over the CC pin that is determined not to be connected to the CC wire as soon as a cable is plugged in. The maximum output power of VCONN is 150mW.
USB BC 1.2 DCP(Dedicated Charging Port) Mode and Quick Charging Legacy
The AP43776Q integrates the USB dedicated charging port auto detect function to recognize most of mainstream portable devices. It supports the following charging schemes like BC1.2 DCP mode, Apple mode, Chinese Telecommunications Industry Standard YD/T 1591-2009, FCP Class A, and Qualcomm Quick Charging HVDCP mode (QC2.0/3.0/4/4+/5).
DisplayPort Alternate Mode Support
The AP43776Q supports DisplayPort Alternate Mode on USB Type-C standard with DP mode Discovery, Enter, Exit included by decoding out the control signals from CC handshaking, and delivering to the mux switches through I2C interface, and then the USB Type-C data stream can be routed to the DP/HDMI receiver correctly. Also, the DP configuration, status update, and source/sink connection detection are provided.
USB BC1.2 CDP Mode
The AP43776Q also supports BC 1.2 CDP (Charging Downstream Port) Mode. It can be enabled by I2C communication. When CDP is enabled, QC/Apple and DCP modes on DP and DM will be turned off.
Bias and Power
The AP43776Q operates from a single external supply source, VCC. VCC is used for analog circuitry and goes through internal regulators to generate all of the voltage and current references for chip operation, without the need for external capacitor decoupling. The AP43776Q has two different power modes: normal and sleep. During normal operation, the AP43771 consumes less than 3mA. During sleep mode, its current can be reduced to around 0.5mA automatically.
I2C Interface
For USB Type-C PD charging system, the I2C interface pins (SCK, SDA) are used to communicate between the PD decoder and DC/DC controller/converter to replace analog signal feedback with much higher noise immunity. The AP43776Q is in charge of the CC1/CC2 or DP/DN protocol handshake with the attached device, and deliver the voltage and current request to DC/DC controller/converter through I2C bus. The AP43776Q, working as an I2C master device, keeps track of charging capability of each USB Type-C port through I2C interface pins at the same time. Based on the user-specified and desired smart power-sharing options for the two charging ports, the AP43776Q decides the final charging profiles for each port. AP43776Q 7 of 13 November 2022 Document number: DS43207 Rev. 2 - 2
www.diodes.com
© Diodes Incorporated