Datasheet AD9696, AD9698 (Analog Devices) - 4
| Fabricante | Analog Devices |
| Descripción | Ultrafast TTL Comparators |
| Páginas / Página | 8 / 4 — AD9696/AD9698. PIN CONFIGURATIONS. OUT (N/C). OUT (LATCH ENABLE 1). Q1OUT … |
| Formato / tamaño de archivo | PDF / 139 Kb |
| Idioma del documento | Inglés |
AD9696/AD9698. PIN CONFIGURATIONS. OUT (N/C). OUT (LATCH ENABLE 1). Q1OUT (–VS). 15 Q2OUT (GROUND). GROUND (–IN. GROUND (Q1OUT)
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AD9696/AD9698 PIN CONFIGURATIONS Q1 Q2 OUT (N/C) 1 16 OUT (LATCH ENABLE 1) Q1OUT (–VS) 2 15 Q2OUT (GROUND) GROUND (–IN 14 1) 3 GROUND (Q1OUT) LATCH ENABLE 1 (+IN 4 13 LATCH ENABLE 2 (Q1 1) TOP VIEW OUT) +VS 8 Q (Not to Scale) 1 OUT N/C (+IN 12 N/C (Q2 2) 5 OUT) +IN 2 7 Q –V 11 +V TOP VIEW OUT S (–IN2) 6 S (Q2OUT) –IN 3 (Not to Scale) 6 GROUND –IN 7 10 –IN 1 (+VS) 2 (GROUND) LATCH –V 4 5 +IN +IN S 1 (N/C) 8 9 2 (LATCH ENABLE 2) ENABLE AD9698KN/KQ/TQ AD9696KN/KR/KQ/TQ/TZ [AD9698KR/TZ PINOUTS SHOWN IN ( )] Name Function
Q1OUT One of two complementary outputs. Q1OUT will be at logic HIGH if voltage at +IN1 is greater than voltage at –IN1 and LATCH ENABLE 1 is at logic LOW. Q1OUT One of two complementary outputs. Q1OUT will be at logic HIGH if voltage at –IN1 is greater than voltage at +IN1 and LATCH ENABLE 1 is at logic LOW. GROUND Analog and digital ground return. All GROUND pins should be connected together and to a low impedance ground plane near the comparator. LATCH Output at Q1OUT will track differential changes at the inputs when LATCH ENABLE 1 is at logic LOW. ENABLE 1 When LATCH ENABLE 1 is at logic HIGH, the output at Q1OUT will reflect the input state at the application of the latch command, delayed by the Latch Enable Setup Time (tS). Since the architecture of the input stage (see block diagram) is faster than the logic of the latch stage, data will typically be latched if applied to the comparator(s) within 1.7 ns after the latch. This is the Setup Time (tS); for guaranteed performance, tS must be 3 ns. N/C No internal connection to comparator. –VS Negative power supply connection; nominally –5.2 V. –IN1 Inverting input of differential input stage for Comparator #1. +IN1 Noninverting input of differential input stage for Comparator #1. +IN2 Noninverting input of differential input stage for Comparator #2. –IN2 Inverting input of differential input stage for Comparator #2. +VS Positive power supply connection; nominally +5 V. LATCH Output at Q2OUT will track differential changes at the inputs when LATCH ENABLE 2 is at logic LOW. ENABLE 2 When LATCH ENABLE 2 is at logic HIGH, the output at Q2OUT will reflect the input state at the application of the latch command, delayed by the Latch Enable Setup Time (tS). Since the architecture of the input stage (see block diagram) is faster than the logic of the latch stage, data will typically be latched if applied to the comparator(s) within 1.7 ns after the latch. This is the Setup Time (tS); for guaranteed performance, tS must be 3 ns. Q2OUT One of two complementary outputs. Q2OUT will be at logic HIGH if voltage at –IN2 is greater than voltage at +IN2 and LATCH ENABLE 2 is at logic LOW. Q2OUT One of two complementary outputs. Q2OUT will be at logic HIGH if voltage at +IN2 is greater than voltage at –IN2 and LATCH ENABLE 2 is at logic LOW.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection.
WARNING!
Although the AD9696/AD9698 features proprietary ESD protection circuitry, permanent dam- age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD SENSITIVE DEVICE
ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– REV. B
Q1OUT One of two complementary outputs. Q1OUT will be at logic HIGH if voltage at +IN1 is greater than voltage at –IN1 and LATCH ENABLE 1 is at logic LOW. Q1OUT One of two complementary outputs. Q1OUT will be at logic HIGH if voltage at –IN1 is greater than voltage at +IN1 and LATCH ENABLE 1 is at logic LOW. GROUND Analog and digital ground return. All GROUND pins should be connected together and to a low impedance ground plane near the comparator. LATCH Output at Q1OUT will track differential changes at the inputs when LATCH ENABLE 1 is at logic LOW. ENABLE 1 When LATCH ENABLE 1 is at logic HIGH, the output at Q1OUT will reflect the input state at the application of the latch command, delayed by the Latch Enable Setup Time (tS). Since the architecture of the input stage (see block diagram) is faster than the logic of the latch stage, data will typically be latched if applied to the comparator(s) within 1.7 ns after the latch. This is the Setup Time (tS); for guaranteed performance, tS must be 3 ns. N/C No internal connection to comparator. –VS Negative power supply connection; nominally –5.2 V. –IN1 Inverting input of differential input stage for Comparator #1. +IN1 Noninverting input of differential input stage for Comparator #1. +IN2 Noninverting input of differential input stage for Comparator #2. –IN2 Inverting input of differential input stage for Comparator #2. +VS Positive power supply connection; nominally +5 V. LATCH Output at Q2OUT will track differential changes at the inputs when LATCH ENABLE 2 is at logic LOW. ENABLE 2 When LATCH ENABLE 2 is at logic HIGH, the output at Q2OUT will reflect the input state at the application of the latch command, delayed by the Latch Enable Setup Time (tS). Since the architecture of the input stage (see block diagram) is faster than the logic of the latch stage, data will typically be latched if applied to the comparator(s) within 1.7 ns after the latch. This is the Setup Time (tS); for guaranteed performance, tS must be 3 ns. Q2OUT One of two complementary outputs. Q2OUT will be at logic HIGH if voltage at –IN2 is greater than voltage at +IN2 and LATCH ENABLE 2 is at logic LOW. Q2OUT One of two complementary outputs. Q2OUT will be at logic HIGH if voltage at +IN2 is greater than voltage at –IN2 and LATCH ENABLE 2 is at logic LOW.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection.
WARNING!
Although the AD9696/AD9698 features proprietary ESD protection circuitry, permanent dam- age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD SENSITIVE DEVICE
ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– REV. B