Datasheet ADG786, ADG788 (Analog Devices) - 10

ADG786/ADG788 VDD VSS VDD VSS 3V LOGIC ADG786/ INPUT (V ADG788 IN) 0V RS S D VOUT C EN* L VS 1nF VOUT V GND V IN OUT QINJ = CL VOUT * IN1–4 for ADG734
Test Circuit 7. Charge Injection
VDD VSS VDD VSS 0.1 F 0.1 F 0.1 F 0.1 F NETWORK NETWORK V V ANALYZER VDD VSS ANALYZER DD SS S 50 S 50 IN 50 IN VS VS D D VOUT V V OUT IN R V L IN RL 50 50 GND GND VOUT VOUT WITH SWITCH OFF ISOLATION = 20 LOG INSERTION LOSS = 20 LOG VS VOUT WITHOUT SWITCH
Test Circuit 8. OFF Isolation Test Circuit 10. Bandwidth
VDD VSS Power Supply Sequencing 0.1 F 0.1 F
When using CMOS devices, care must be taken to ensure cor- rect power supply sequencing. Incorrect sequencing can result
NETWORK ANALYZER V
in the device being subjected to stresses beyond those maximum
DD VSS VOUT
ratings listed in the data sheet. Digital and analog inputs should
SA RL
be applied to the device after supplies and ground. In dual sup-
50 SB D R
ply applications, if digital and analog inputs may be applied
50 50
prior to VDD and VSS supplies, the addition of a Schottky diode
IN V
connected between V
S
SS and GND will ensure that the device
GND
powers on correctly. For single supply applications, VSS should be tied to GND as close to the device as possible.
CHANNEL-TO-CHANNEL VOUT CROSSTALK = 20 LOG VS
Test Circuit 9. Channel-to-Channel Crosstalk –10– REV.$