Datasheet ADG613-EP (Analog Devices) - 5
| Fabricante | Analog Devices |
| Descripción | 1 pC Charge Injection, 100 pA Leakage, CMOS, ±5 V/ +5 V/ +3 V, Quad SPST Switches |
| Páginas / Página | 12 / 5 — Enhanced Product. ADG613-EP. Table 3. Parameter. 25°C. −55°C to +125°C. … |
| Revisión | A |
| Formato / tamaño de archivo | PDF / 258 Kb |
| Idioma del documento | Inglés |
Enhanced Product. ADG613-EP. Table 3. Parameter. 25°C. −55°C to +125°C. Unit. Test Conditions/Comments
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Enhanced Product ADG613-EP
VDD = 3 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. VS is the source voltage. VD is the drain voltage.
Table 3. Parameter 25°C −55°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH Analog Signal Range 0 to VDD V On Resistance, RON 380 460 Ω typ VS = 1.5 V, IS = −1 mA; see Figure 14 LEAKAGE CURRENTS VDD = 3.3 V Source Off Leakage, IS(OFF) ±0.01 nA typ VS = 1 V or 3 V, VD = 3 V or 1 V; see Figure 15 ±0.1 ±2 nA max VS = 1 V or 3 V, VD = 3 V or 1 V; see Figure 15 Drain Off Leakage, ID(OFF) ±0.01 nA typ VS = 1 V or 3 V, VD = 3 V or 1 V; see Figure 15 ±0.1 ±2 nA max VS = 1 V or 3 V, VD = 3 V or 1 V; see Figure 15 Channel On Leakage, ID(ON), IS(ON) ±0.01 nA typ VS = VD = 1 V or 3 V; see Figure 16 ±0.1 ±6 nA max VS = VD = 1 V or 3 V; see Figure 16 DIGITAL INPUTS Input High Voltage, VINH 2.0 V min Input Low Voltage, VINL 0.8 V max Input Current, IINL or IINH 0.005 μA typ VIN = VINL or VINH ±0.1 μA max VIN = VINL or VINH Digital Input Capacitance, CIN 2 pF typ DYNAMIC CHARACTERISTICS1 tON 130 ns typ RL = 300 Ω, CL = 35 pF, VS = 2 V; see Figure 17 185 260 ns max RL = 300 Ω, CL = 35 pF, VS = 2 V; see Figure 17 tOFF 40 ns typ RL = 300 Ω, CL = 35 pF, VS = 2 V; see Figure 17 55 65 ns max RL = 300 Ω, CL = 35 pF, VS = 2 V; see Figure 17 Break-Before-Make Time Delay, tBBM 50 ns typ RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 2 V; see Figure 18 10 ns min RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 2 V; see Figure 18 Charge Injection 1.5 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 19 Off Isolation −62 dB typ RL = 50 Ω, CL = 5 pF, f = 10 MHz; see Figure 20 Channel to Channel Crosstalk −90 dB typ RL = 50 Ω, CL = 5 pF, f = 10 MHz; see Figure 21 −3 dB Bandwidth 680 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 22 CS(OFF) 5 pF typ f = 1 MHz CD(OFF) 5 pF typ f = 1 MHz CD(ON), CS(ON) 5 pF typ f = 1 MHz POWER REQUIREMENTS VDD = 3.3 V IDD 0.001 μA typ Digital inputs = 0 V or 3.3 V 1.0 μA max Digital inputs = 0 V or 3.3 V VDD 2.7 V min 5.5 V max Power Consumption 3.3 nW typ 3.3 µW max 1 Guaranteed by design; not subject to production test. Rev. A | Page 5 of 12 Document Outline FEATURES ENHANCED PRODUCT FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS DUAL-SUPPLY OPERATION SINGLE-SUPPLY OPERATION ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE
Enhanced Product ADG613-EP
VDD = 3 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. VS is the source voltage. VD is the drain voltage.
Table 3. Parameter 25°C −55°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH Analog Signal Range 0 to VDD V On Resistance, RON 380 460 Ω typ VS = 1.5 V, IS = −1 mA; see Figure 14 LEAKAGE CURRENTS VDD = 3.3 V Source Off Leakage, IS(OFF) ±0.01 nA typ VS = 1 V or 3 V, VD = 3 V or 1 V; see Figure 15 ±0.1 ±2 nA max VS = 1 V or 3 V, VD = 3 V or 1 V; see Figure 15 Drain Off Leakage, ID(OFF) ±0.01 nA typ VS = 1 V or 3 V, VD = 3 V or 1 V; see Figure 15 ±0.1 ±2 nA max VS = 1 V or 3 V, VD = 3 V or 1 V; see Figure 15 Channel On Leakage, ID(ON), IS(ON) ±0.01 nA typ VS = VD = 1 V or 3 V; see Figure 16 ±0.1 ±6 nA max VS = VD = 1 V or 3 V; see Figure 16 DIGITAL INPUTS Input High Voltage, VINH 2.0 V min Input Low Voltage, VINL 0.8 V max Input Current, IINL or IINH 0.005 μA typ VIN = VINL or VINH ±0.1 μA max VIN = VINL or VINH Digital Input Capacitance, CIN 2 pF typ DYNAMIC CHARACTERISTICS1 tON 130 ns typ RL = 300 Ω, CL = 35 pF, VS = 2 V; see Figure 17 185 260 ns max RL = 300 Ω, CL = 35 pF, VS = 2 V; see Figure 17 tOFF 40 ns typ RL = 300 Ω, CL = 35 pF, VS = 2 V; see Figure 17 55 65 ns max RL = 300 Ω, CL = 35 pF, VS = 2 V; see Figure 17 Break-Before-Make Time Delay, tBBM 50 ns typ RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 2 V; see Figure 18 10 ns min RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 2 V; see Figure 18 Charge Injection 1.5 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 19 Off Isolation −62 dB typ RL = 50 Ω, CL = 5 pF, f = 10 MHz; see Figure 20 Channel to Channel Crosstalk −90 dB typ RL = 50 Ω, CL = 5 pF, f = 10 MHz; see Figure 21 −3 dB Bandwidth 680 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 22 CS(OFF) 5 pF typ f = 1 MHz CD(OFF) 5 pF typ f = 1 MHz CD(ON), CS(ON) 5 pF typ f = 1 MHz POWER REQUIREMENTS VDD = 3.3 V IDD 0.001 μA typ Digital inputs = 0 V or 3.3 V 1.0 μA max Digital inputs = 0 V or 3.3 V VDD 2.7 V min 5.5 V max Power Consumption 3.3 nW typ 3.3 µW max 1 Guaranteed by design; not subject to production test. Rev. A | Page 5 of 12 Document Outline FEATURES ENHANCED PRODUCT FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS DUAL-SUPPLY OPERATION SINGLE-SUPPLY OPERATION ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE