Datasheet ADG613-EP (Analog Devices) - 10
| Fabricante | Analog Devices |
| Descripción | 1 pC Charge Injection, 100 pA Leakage, CMOS, ±5 V/ +5 V/ +3 V, Quad SPST Switches |
| Páginas / Página | 12 / 10 — ADG613-EP. Enhanced Product. TEST CIRCUITS. IS(OFF). ID(OFF). ID(ON). RON … |
| Revisión | A |
| Formato / tamaño de archivo | PDF / 258 Kb |
| Idioma del documento | Inglés |
ADG613-EP. Enhanced Product. TEST CIRCUITS. IS(OFF). ID(OFF). ID(ON). RON = V1/IDS. NC = NO CONNECT. VDD. VSS. 0.1µF. VIN2, VIN3. 50%. VOUT. 300Ω
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ADG613-EP Enhanced Product TEST CIRCUITS IS(OFF) ID(OFF) Sx Dx A A V I S VD DS
015 14533-
V1
Figure 15. Off Leakage
ID(ON) Sx Dx Sx Dx NC A VS RON = V1/IDS VD
014
NC = NO CONNECT
016 14533- 14533- Figure 14. On Resistance Figure 16. On Leakage
VDD VSS 0.1µF 0.1µF VIN2, VIN3 50% 50% VDD VSS VOUT Sx Dx 50% 50% RL CL V V S 300Ω IN1, VIN4 35pF INx 90% 90% VOUT GND t
017
ON tOFF
14533- Figure 17. Switching Times
VDD VSS 0.1µF 0.1µF VIN 50% 50% 0V VDD VSS 90% 90% V V S1 D1 OUT1 S1 VOUT1 0V RL1 CL1 V S2 D2 S2 VOUT2 300Ω 35pF RL2 CL2 90% 35pF 90% 300Ω VOUT2 V IN1, IN IN2 ADG613-EP 0V GND
018
tBBM tBBM
14533- Figure 18. Break-Before-Make Time Delay
VDD VSS VIN2, VIN3 VDD VSS R VOUT S Sx Dx ON OFF V C S L 1nF V INx IN1, VIN4 V GND OUT Q ΔV INJ = CL × ΔVOUT OUT
019 14533- Figure 19. Charge Injection Rev. A | Page 10 of 12 Document Outline FEATURES ENHANCED PRODUCT FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS DUAL-SUPPLY OPERATION SINGLE-SUPPLY OPERATION ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE
015 14533-
V1
Figure 15. Off Leakage
ID(ON) Sx Dx Sx Dx NC A VS RON = V1/IDS VD
014
NC = NO CONNECT
016 14533- 14533- Figure 14. On Resistance Figure 16. On Leakage
VDD VSS 0.1µF 0.1µF VIN2, VIN3 50% 50% VDD VSS VOUT Sx Dx 50% 50% RL CL V V S 300Ω IN1, VIN4 35pF INx 90% 90% VOUT GND t
017
ON tOFF
14533- Figure 17. Switching Times
VDD VSS 0.1µF 0.1µF VIN 50% 50% 0V VDD VSS 90% 90% V V S1 D1 OUT1 S1 VOUT1 0V RL1 CL1 V S2 D2 S2 VOUT2 300Ω 35pF RL2 CL2 90% 35pF 90% 300Ω VOUT2 V IN1, IN IN2 ADG613-EP 0V GND
018
tBBM tBBM
14533- Figure 18. Break-Before-Make Time Delay
VDD VSS VIN2, VIN3 VDD VSS R VOUT S Sx Dx ON OFF V C S L 1nF V INx IN1, VIN4 V GND OUT Q ΔV INJ = CL × ΔVOUT OUT
019 14533- Figure 19. Charge Injection Rev. A | Page 10 of 12 Document Outline FEATURES ENHANCED PRODUCT FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS DUAL-SUPPLY OPERATION SINGLE-SUPPLY OPERATION ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE