Datasheet ADGS5412 (Analog Devices) - 10

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ADGS5412 Data Sheet Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
DYNAMIC CHARACTERISTICS1 tON 470 ns typ RL = 300 Ω, CL = 35 pF 555 565 580 ns max VS = 18 V; see Figure 36 tOFF 195 ns typ RL = 300 Ω, CL = 35 pF 245 250 260 ns max VS = 18 V; see Figure 36 Break-Before-Make Time Delay, tD 245 ns typ RL = 300 Ω, CL = 35 pF 185 ns min VS1 = VS2 = 18 V, see Figure 35 Charge Injection, QINJ 285 pC typ VS = 18 V, RS = 0 Ω, CL = 1 nF; see Figure 37 Off Isolation −78 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 31 Channel-to-Channel Crosstalk −70 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 30 Total Harmonic Distortion + Noise, 0.03 % typ RL = 1 kΩ, 18 V p-p, f = 20 Hz to THD + N 20 kHz; see Figure 33 −3 dB Bandwidth 174 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 34 Insertion Loss −0.7 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 34 Off Switch Source Capacitance, 17 pF typ VS = 18 V, f = 1 MHz CS (Off) Off Switch Drain Capacitance, 17 pF typ VS = 18 V, f = 1 MHz CD (Off) On Switch Capacitance, CD (On), 55 pF typ VS = 18 V, f = 1 MHz CS (On) POWER REQUIREMENTS VDD = 39.6 V Positive Supply Current, IDD 80 µA typ Digital inputs = 0 V or VL 100 130 µA max 80 µA typ All switches closed, VL = 5.5 V 135 µA typ All switches closed, VL = 2.7 V IL Inactive 6.3 µA typ Digital inputs = 0 V or VL 8.0 µA max Inactive, SCLK = 1 MHz 14 µA typ CS = VL and SDI = 0 V or VL, VL = 5 V 7 µA typ CS = VL and SDI = 0 V or VL, VL = 3 V SCLK = 50 MHz 390 µA typ CS = VL and SDI = 0 V or VL, VL = 5 V 210 µA typ CS = VL and SDI = 0 V or VL, VL = 3 V Inactive, SDI = 1 MHz 15 µA typ CS and SCLK = 0 V or VL, VL = 5 V 7.5 µA typ CS and SCLK = 0 V or VL, VL = 3 V SDI = 25 MHz 230 µA typ CS and SCLK = 0 V or VL, VL = 5 V 120 µA typ CS and SCLK = 0 V or VL, VL = 3 V Active at 50 MHz 1.8 mA typ Digital inputs toggle between 0 V and VL, VL = 5.5 V 2.1 mA max 0.7 mA typ Digital inputs toggle between 0 V and VL, VL = 2.7 V 1.0 mA max VDD 9/40 V min/V max GND = 0 V, VSS = 0 V 1 Guaranteed by design; not subject to production test. Rev. A | Page 10 of 30 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ±15 V DUAL SUPPLY ±20 V DUAL SUPPLY 12 V SINGLE SUPPLY 36 V SINGLE SUPPLY CONTINUOUS CURRENT PER CHANNEL, SX OR DX TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS TERMINOLOGY THEORY OF OPERATION ADDRESS MODE ERROR DETECTION FEATURES Cyclic Redundancy Check (CRC) Error Detection SCLK Count Error Detection Invalid Read/Write Address Error CLEARING THE ERROR FLAGS REGISTER BURST MODE SOFTWARE RESET DAISY-CHAIN MODE POWER-ON RESET BREAK-BEFORE-MAKE SWITCHING TRENCH ISOLATION DIGITAL INPUT BUFFERS APPLICATIONS INFORMATION POWER SUPPLY RAILS POWER SUPPLY RECOMMENDATIONS REGISTER SUMMARY REGISTER DETAILS SWITCH DATA REGISTER Address: 0x01, Reset: 0x00, Name: SW_DATA ERROR CONFIGURATION REGISTER Address: 0x02, Reset: 0x06, Name: ERR_CONFIG ERROR FLAGS REGISTER Address: 0x03, Reset: 0x00, Name: ERR_FLAGS BURST ENABLE REGISTER Address: 0x05, Reset: 0x00, Name: BURST_EN SOFTWARE RESET REGISTER Address: 0x0B, Reset: 0x00, Name: SOFT_RESETB OUTLINE DIMENSIONS ORDERING GUIDE