Datasheet ADGS5412 (Analog Devices)

SPI Interface, 4× SPST Switches, 9.8 Ω RON, ±20 V/+36 V, Mux Configurable Data Sheet ADGS5412 FEATURES FUNCTIONAL BLOCK DIAGRAM SPI interface with error detection ADGS5412 Includes CRC, invalid read/write address, and SCLK count error detection S1 D1 Supports burst mode and daisy-chain mode Industry standard SPI Mode 0 and Mode 3 interface S2 D2 compatible Guaranteed break-before-make switching allowing external S3 D3 wiring of switches to deliver multiplexer configurations V S4 D4 SS to VDD analog signal range Fully specified at ±15 V, ±20 V, +12 V, and +36 V ±9 V to ±22 V dual-supply operation SPI SDO 9 V to 40 V single-supply operation INTERFACE Latch-up proof analog switch pins
1
8 kV HBM ESD rating
-00
SCLK SDI CS RESET/VL
234
Low on resistance (<10 Ω)
15
1.8 V logic compatibility with 2.7 V ≤ V
Figure 1.
L ≤ 3.3 V APPLICATIONS Relay replacement Automatic test equipment Data acquisition Instrumentation Avionics Audio and video switching Communication systems GENERAL DESCRIPTION
The ADGS5412 contains four independent single-pole/single- applications with external wiring. throw (SPST) switches. A serial peripheral interface (SPI) controls
PRODUCT HIGHLIGHTS
the switches. The SPI interface has robust error detection features, including cyclic redundancy check (CRC) error detection, invalid 1. SPI interface removes the need for parallel conversion and read/write address detection, and serial clock (SCLK) count logic traces and reduces general-purpose input/output error detection. (GPIO) channel count. It is possible to daisy-chain multiple ADGS5412 devices together, 2. Daisy-chain mode removes additional logic traces when which enables the configuration of multiple devices with a multiple devices are used. minimal amount of digital lines. The ADGS5412 can also 3. CRC, invalid read/write address, and SCLK count error operate in burst mode to decrease the time between SPI detection ensure a robust digital interface. commands. 4. CRC error detection capabilities allow for the use of the ADGS5412 in safety critical systems. Each switch conducts equally well in both directions when on, 5. Guaranteed break-before-make switching allows the use of and each switch has an input signal range that extends to the the ADGS5412 in multiplexer configurations with external supplies. In the off condition, signal levels up to the supplies are wiring. blocked. The on-resistance profile is very flat over the full analog input Trench isolation analog switch section guards against latch-up. A range, which ensures good linearity and low distortion when dielectric trench separates the positive (P) and negative (N) channel switching audio signals. The ADGS5412 exhibits break-before- transistors thereby preventing latch-up even under severe make switching action, allowing use of the device in multiplexer overvoltage conditions.
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Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ±15 V DUAL SUPPLY ±20 V DUAL SUPPLY 12 V SINGLE SUPPLY 36 V SINGLE SUPPLY CONTINUOUS CURRENT PER CHANNEL, SX OR DX TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS TERMINOLOGY THEORY OF OPERATION ADDRESS MODE ERROR DETECTION FEATURES Cyclic Redundancy Check (CRC) Error Detection SCLK Count Error Detection Invalid Read/Write Address Error CLEARING THE ERROR FLAGS REGISTER BURST MODE SOFTWARE RESET DAISY-CHAIN MODE POWER-ON RESET BREAK-BEFORE-MAKE SWITCHING TRENCH ISOLATION DIGITAL INPUT BUFFERS APPLICATIONS INFORMATION POWER SUPPLY RAILS POWER SUPPLY RECOMMENDATIONS REGISTER SUMMARY REGISTER DETAILS SWITCH DATA REGISTER Address: 0x01, Reset: 0x00, Name: SW_DATA ERROR CONFIGURATION REGISTER Address: 0x02, Reset: 0x06, Name: ERR_CONFIG ERROR FLAGS REGISTER Address: 0x03, Reset: 0x00, Name: ERR_FLAGS BURST ENABLE REGISTER Address: 0x05, Reset: 0x00, Name: BURST_EN SOFTWARE RESET REGISTER Address: 0x0B, Reset: 0x00, Name: SOFT_RESETB OUTLINE DIMENSIONS ORDERING GUIDE