Datasheet ADGS1612 (Analog Devices) - 3

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Data Sheet ADGS1612 SPECIFICATIONS ±5 V DUAL SUPPLY
Positive supply (VDD) = 5 V ± 10%, negative supply (VSS) = −5 V ± 10%, digital supply (VL) = 2.7 V to 5.5 V, GND = 0 V, unless otherwise noted.
Table 1. Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH Analog Signal Range VDD to VSS V On Resistance, RON 1 Ω typ VS = ±4.5 V, IS = −10 mA; see Figure 29 1.2 1.4 1.6 Ω max VDD = +4.5 V, VSS = −4.5 V On Resistance Match Between 0.04 Ω typ VS = ±4.5 V, IS = −10 mA Channels, ∆RON 0.08 0.09 0.1 Ω max On Resistance Flatness, RFLAT (ON) 0.23 Ω typ VS = ±4.5 V, IS = −10 mA 0.28 0.32 0.37 Ω max LEAKAGE CURRENTS VDD = +5.5 V, VSS = −5.5 V Source Off Leakage, IS (Off ) ±0.1 nA typ VS = ±4.5 V, VD = ∓4.5 V; see Figure 32 ±0.3 ±1.0 ±6.0 nA max Drain Off Leakage, ID (Off ) ±0.1 nA typ VS = ±4.5 V, VD = ∓4.5 V; see Figure 32 ±0.3 ±1.0 ±6.0 nA max Channel On Leakage, ID (On), IS (On) ±0.2 nA typ VS = VD = ±4.5 V; see Figure 28 ±0.4 ±1.5 ±10.0 nA max DIGITAL OUTPUT Output Voltage Low, VOL 0.4 V max ISINK = 5 mA 0.2 V max ISINK = 1 mA Output Current, Low (IOL) or High (IOH) 0.001 μA typ VOUT = VGND or VL ±0.1 μA max Digital Output Capacitance, COUT 4 pF typ DIGITAL INPUTS Input Voltage High, VINH 2 V min 3.3 V < VL ≤ 5.5 V 1.35 V min 2.7 V ≤ VL ≤ 3.3 V Low, VINL 0.8 V max 3.3 V < VL ≤ 5.5 V 0.8 V max 2.7 V ≤ VL ≤ 3.3 V Input Current, Low (IINL) or High (IINH) 0.001 μA typ VIN = VGND or VL ±0.1 μA max Digital Input Capacitance, CIN 4 pF typ DYNAMIC CHARACTERISTICS On Time, tON 385 ns typ RL = 300 Ω, CL = 35 pF 480 485 485 ns max VS = 2.5 V; see Figure 36 Off Time, tOFF 250 ns typ RL = 300 Ω, CL = 35 pF 305 335 360 ns max VS = 2.5 V; see Figure 36 Break-Before-Make Time Delay, tD 175 ns typ RL = 300 Ω, CL = 35 pF 115 ns min VS1 = VS2 = 2.5 V, see Figure 35 Charge Injection, QINJ 120 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 37 Off Isolation −65 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 31 Channel to Channel Crosstalk −93 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 30 Rev. 0 | Page 3 of 29 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Revision History Specifications ±5 V Dual Supply 12 V Single Supply 5 V Single Supply 3.3 V Single Supply Continuous Current per Channel, Sx or Dx Timing Characteristics Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Test Circuits Terminology Theory of Operation Address Mode Error Detection Features Cyclic Redundancy Check (CRC) Error Detection SCLK Count Error Detection Invalid Read/Write Address Error Clearing the Error Flags Register Burst Mode Software Reset Daisy-Chain Mode Power-On Reset Applications Information Break-Before-Make Switching Digital Input Buffers Power Supply Rails Register Summary Register Details Switch Data Register Address: 0x01, Reset: 0x00, Name: SW_DATA Error Configuration Register Address: 0x02, Reset: 0x06, Name: ERR_CONFIG Error Flags Register Address: 0x03, Reset: 0x00, Name: ERR_FLAGS Burst Enable Register Address: 0x05, Reset: 0x00, Name: BURST_EN Software Reset Register Address: 0x0B, Reset: 0x00, Name: SOFT_RESETB Outline Dimensions Ordering Guide