Datasheet AEM00330 (E-peas) - 3
| Fabricante | E-peas |
| Descripción | Highly Versatile Buck-Boost Ambient Energy Manager with Source Voltage Level Configuration |
| Páginas / Página | 30 / 3 — DATASHEET. AEM00330. List of Figures |
| Formato / tamaño de archivo | PDF / 896 Kb |
| Idioma del documento | Inglés |
DATASHEET. AEM00330. List of Figures
Línea de modelo para esta hoja de datos
Versión de texto del documento
link to page 5 link to page 6 link to page 11 link to page 12 link to page 14 link to page 16 link to page 18 link to page 21 link to page 22 link to page 24 link to page 24 link to page 25 link to page 25 link to page 26 link to page 26 link to page 27 link to page 28 link to page 29 link to page 30
DATASHEET AEM00330 List of Figures
Figure 1: Simplified Schematic View . 5 Figure 2: Pinout Diagram QFN 40-pin . 6 Figure 3: Functional Block Diagram . .11 Figure 4: Simplified Schematic View of the AEM00330 . .12 Figure 5: Diagram of the AEM00330 States . 14 Figure 6: Maximum LOAD Current Depending on VSTO and on VLOAD . .16 Figure 7: Custom Mode Settings . .18 Figure 8: Typical Application Circuit 1 . 21 Figure 9: Typical Application Circuit 2 . 22 Figure 10: Wake-up state, Start state and Supply state . 24 Figure 11: Wake-up state, Start state and Supply state . 24 Figure 12: DCDC Efficiency from SRC to STO for 1 mA and 10 mA in Low Power Mode . .25 Figure 13: DCDC Efficiency from SRC to STO for 10 mA and 50 mA in High Power Mode . 25 Figure 14: DCDC Efficiency from STO to LOAD in Low Power Mode . 26 Figure 15: DCDC Efficiency from STO to LOAD in High Power Mode . 26 Figure 16: Schematic Example . 27 Figure 17: Layout Example for the AEM00330 and its Passive Components . .28 Figure 18: QFN 40-pin 5x5mm Drawing (Al Dimensions in mm) . 29 Figure 19: Recommended Board Layout for QFN40 package (Al Dimensions in mm) . 30 DS_AEM00330_Rev1.0 Copyright © 2022 e-peas SA Confidential 3 Document Outline Table of Contents List of Tables 1. Introduction 2. Absolute Maximum Ratings 3. Thermal Resistance 4. Typical Electrical Characteristics at 25 °C 5. Recommended Operation Conditions 6. Functional Block Diagram 7. Theory of Operation 7.1. DCDC Converter 7.2. Reset, Wake Up and Start States 7.2.1. Storage Element Priority Supercapacitor as a Storage Element Battery as a Storage Element 7.2.2. Load Priority 7.3. Supply State 7.4. Shutdown State 7.5. Sleep State 7.6. Source Voltage Regulation 7.7. Balancing for Dual-Cell Supercapacitor 8. System Configuration 8.1. High Power / Low Power Mode 8.2. Storage Element Configuration 8.3. Load Configuration 8.4. Custom Mode Configuration 8.5. Disable Storage Element Charging 8.6. Source Level Configuration 8.7. External Components 8.7.1. Storage element information 8.7.2. External inductor information 8.7.3. External capacitors information CSRC CINT CLOAD 9. Typical Application Circuits 9.1. Example Circuit 1 9.2. Example Circuit 2 9.3. Circuit Behaviour 9.4. DCDC Conversion Efficiency From SRC to STO in Low Power Mode 9.4. DCDC Conversion Efficiency From SRC to STO in Low Power Mode 9.5. DCDC Conversion Efficiency From SRC to STO in High Power Mode 9.6. DCDC Conversion Efficiency From STO to LOAD in Low Power Mode 9.7. DCDC Conversion Efficiency From STO to LOAD in High Power Mode 10. Schematic 11. Layout 12. Package Information 12.1. Plastic Quad Flatpack No-Lead (QFN 40-pin 5x5mm) 12.2. Board Layout 13. Revision History
DATASHEET AEM00330 List of Figures
Figure 1: Simplified Schematic View . 5 Figure 2: Pinout Diagram QFN 40-pin . 6 Figure 3: Functional Block Diagram . .11 Figure 4: Simplified Schematic View of the AEM00330 . .12 Figure 5: Diagram of the AEM00330 States . 14 Figure 6: Maximum LOAD Current Depending on VSTO and on VLOAD . .16 Figure 7: Custom Mode Settings . .18 Figure 8: Typical Application Circuit 1 . 21 Figure 9: Typical Application Circuit 2 . 22 Figure 10: Wake-up state, Start state and Supply state . 24 Figure 11: Wake-up state, Start state and Supply state . 24 Figure 12: DCDC Efficiency from SRC to STO for 1 mA and 10 mA in Low Power Mode . .25 Figure 13: DCDC Efficiency from SRC to STO for 10 mA and 50 mA in High Power Mode . 25 Figure 14: DCDC Efficiency from STO to LOAD in Low Power Mode . 26 Figure 15: DCDC Efficiency from STO to LOAD in High Power Mode . 26 Figure 16: Schematic Example . 27 Figure 17: Layout Example for the AEM00330 and its Passive Components . .28 Figure 18: QFN 40-pin 5x5mm Drawing (Al Dimensions in mm) . 29 Figure 19: Recommended Board Layout for QFN40 package (Al Dimensions in mm) . 30 DS_AEM00330_Rev1.0 Copyright © 2022 e-peas SA Confidential 3 Document Outline Table of Contents List of Tables 1. Introduction 2. Absolute Maximum Ratings 3. Thermal Resistance 4. Typical Electrical Characteristics at 25 °C 5. Recommended Operation Conditions 6. Functional Block Diagram 7. Theory of Operation 7.1. DCDC Converter 7.2. Reset, Wake Up and Start States 7.2.1. Storage Element Priority Supercapacitor as a Storage Element Battery as a Storage Element 7.2.2. Load Priority 7.3. Supply State 7.4. Shutdown State 7.5. Sleep State 7.6. Source Voltage Regulation 7.7. Balancing for Dual-Cell Supercapacitor 8. System Configuration 8.1. High Power / Low Power Mode 8.2. Storage Element Configuration 8.3. Load Configuration 8.4. Custom Mode Configuration 8.5. Disable Storage Element Charging 8.6. Source Level Configuration 8.7. External Components 8.7.1. Storage element information 8.7.2. External inductor information 8.7.3. External capacitors information CSRC CINT CLOAD 9. Typical Application Circuits 9.1. Example Circuit 1 9.2. Example Circuit 2 9.3. Circuit Behaviour 9.4. DCDC Conversion Efficiency From SRC to STO in Low Power Mode 9.4. DCDC Conversion Efficiency From SRC to STO in Low Power Mode 9.5. DCDC Conversion Efficiency From SRC to STO in High Power Mode 9.6. DCDC Conversion Efficiency From STO to LOAD in Low Power Mode 9.7. DCDC Conversion Efficiency From STO to LOAD in High Power Mode 10. Schematic 11. Layout 12. Package Information 12.1. Plastic Quad Flatpack No-Lead (QFN 40-pin 5x5mm) 12.2. Board Layout 13. Revision History