Datasheet NCP502, NCV502 (ON Semiconductor) - 9
| Fabricante | ON Semiconductor |
| Descripción | Voltage Regulator - CMOS Low Iq, Low-Dropout 80 mA |
| Páginas / Página | 10 / 9 — PACKAGE DIMENSIONS. TSOP−5. SCALE 2:1. NOTE 5. D 5X. DETAIL Z. … |
| Revisión | 21 |
| Formato / tamaño de archivo | PDF / 285 Kb |
| Idioma del documento | Inglés |
PACKAGE DIMENSIONS. TSOP−5. SCALE 2:1. NOTE 5. D 5X. DETAIL Z. MILLIMETERS. TOP VIEW. DIM. MIN. MAX. C SEATING. END VIEW. PLANE. SIDE VIEW. GENERIC
Línea de modelo para esta hoja de datos
- NCP502SN28T1G NCP502SN29T1G NCP502SN30T1G NCP502SN31T1G NCP502SN33T1G NCP502SN34T1G NCP502SN35T1G NCP502SN36T1G NCP502SN37T1G NCP502SN50T1G NCP502SQ15T2G NCP502SQ18T2G NCP502SQ25T2G NCP502SQ27T2G NCP502SQ28T2G NCP502SQ29T2G NCP502SQ30T2G NCP502SQ31T2G NCP502SQ33T2G NCP502SQ34T2G NCP502SQ35T2G NCP502SQ36T2G NCP502SQ37T2G NCP502SQ50T2G NCV502SN33T1G NCV502SN50T1G
Versión de texto del documento
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS TSOP−5
CASE 483 5 ISSUE N 1 DATE 12 AUG 2020
SCALE 2:1
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME
NOTE 5
Y14.5M, 1994.
D 5X
2. CONTROLLING DIMENSION: MILLIMETERS. 0.20 C A B 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
2X
0.10 T THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.
M
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
5 4
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
2X
0.20 T
B S
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
1 2 3
EXCEED 0.15 PER SIDE. DIMENSION A.
K
5. OPTIONAL CONSTRUCTION: AN ADDITIONAL TRIMMED LEAD IS ALLOWED IN THIS LOCATION.
B G DETAIL Z
TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2 FROM BODY.
A A MILLIMETERS TOP VIEW DIM MIN MAX A
2.85 3.15
B
1.35 1.65
DETAIL Z C
0.90 1.10
D
0.25 0.50
J G
0.95 BSC
C H
0.01 0.10 0.05
J
0.10 0.26
H K
0.20 0.60
C SEATING END VIEW PLANE M
0 10 _ _
SIDE VIEW S
2.50 3.00
GENERIC SOLDERING FOOTPRINT* MARKING DIAGRAM*
1.9 0.074 5 5 0.95 XXXAYWG XXX MG 0.037 G G 1 1
Analog Discrete/Logic
2.4 XXX = Specific Device Code XXX = Specific Device Code 0.094 A = Assembly Location M = Date Code Y = Year G = Pb−Free Package 1.0 W = Work Week 0.039 G = Pb−Free Package (Note: Microdot may be in either location) 0.7 *This information is generic. Please refer to 0.028 SCALE 10:1 ǒ mm Ǔ inches device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, *For additional information on our Pb−Free strategy and soldering may or may not be present. details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER: 98ARB18753C
Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DESCRIPTION: TSOP−5 PAGE 1 OF 1
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com
PACKAGE DIMENSIONS TSOP−5
CASE 483 5 ISSUE N 1 DATE 12 AUG 2020
SCALE 2:1
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME
NOTE 5
Y14.5M, 1994.
D 5X
2. CONTROLLING DIMENSION: MILLIMETERS. 0.20 C A B 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
2X
0.10 T THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.
M
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
5 4
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
2X
0.20 T
B S
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
1 2 3
EXCEED 0.15 PER SIDE. DIMENSION A.
K
5. OPTIONAL CONSTRUCTION: AN ADDITIONAL TRIMMED LEAD IS ALLOWED IN THIS LOCATION.
B G DETAIL Z
TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2 FROM BODY.
A A MILLIMETERS TOP VIEW DIM MIN MAX A
2.85 3.15
B
1.35 1.65
DETAIL Z C
0.90 1.10
D
0.25 0.50
J G
0.95 BSC
C H
0.01 0.10 0.05
J
0.10 0.26
H K
0.20 0.60
C SEATING END VIEW PLANE M
0 10 _ _
SIDE VIEW S
2.50 3.00
GENERIC SOLDERING FOOTPRINT* MARKING DIAGRAM*
1.9 0.074 5 5 0.95 XXXAYWG XXX MG 0.037 G G 1 1
Analog Discrete/Logic
2.4 XXX = Specific Device Code XXX = Specific Device Code 0.094 A = Assembly Location M = Date Code Y = Year G = Pb−Free Package 1.0 W = Work Week 0.039 G = Pb−Free Package (Note: Microdot may be in either location) 0.7 *This information is generic. Please refer to 0.028 SCALE 10:1 ǒ mm Ǔ inches device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, *For additional information on our Pb−Free strategy and soldering may or may not be present. details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER: 98ARB18753C
Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DESCRIPTION: TSOP−5 PAGE 1 OF 1
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com