Datasheet ADSP-TS101S (Analog Devices) - 7

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ADSP-TS101S Host Interface
The SDRAM interface provides a glueless interface with stan- dard SDRAMs—16M bit, 64M bit, 128M bit, and 256M bit. The The ADSP-TS101S provides an easy and configurable interface DSP directly supports a maximum of 64M words  32 bits of between its external bus and host processors through the exter- SDRAM. The SDRAM interface is mapped in external memory nal port. To accommodate a variety of host processors, the host in the DSP’s unified memory map. interface supports pipelined or slow protocols for accesses of the host as slave. Each protocol has programmable transmission
EPROM Interface
parameters, such as idle cycles, pipe depth, and internal wait cycles. The ADSP-TS101S can be configured to boot from external 8-bit EPROM at reset through the external port. An automatic The host interface supports burst transactions initiated by a host process (which follows reset) loads a program from the EPROM processor. After the host issues the starting address of the burst into internal memory. This process uses 16 wait cycles for each and asserts the BRST signal, the DSP increments the address read access. During booting, the BMS pin functions as the internally while the host continues to assert BRST. EPROM chip select signal. The EPROM boot procedure uses The host interface provides a deadlock recovery mechanism that DMA Channel 0, which packs the bytes into 32-bit instructions. enables a host to recover from deadlock situations involving the Applications can also access the EPROM (write flash memories) DSP. The BOFF signal provides the deadlock recovery mecha- during normal operation through DMA. nism. When the host asserts BOFF, the DSP backs off the The EPROM or flash memory interface is not mapped in the current transaction and asserts HBG and relinquishes the exter- DSP’s unified memory map. It is a byte address space limited to nal bus. a maximum of 16M bytes (24 address bits). The EPROM or The host can directly read or write the internal memory of the flash memory interface can be used after boot via a DMA. ADSP-TS101S, and it can access most of the DSP registers, including DMA control (TCB) registers. Vector interrupts sup-
DMA CONTROLLER
port efficient execution of host commands. The ADSP-TS101S processor’s on-chip DMA controller, with 14 DMA channels, provides zero-overhead data transfers with-
Multiprocessor Interface
out processor intervention. The DMA controller operates The ADSP-TS101S offers powerful features tailored to multi- independently and invisibly to the DSP’s core, enabling DMA processing DSP systems through the external port and link operations to occur while the DSP’s core continues to execute ports. This multiprocessing capability provides highest band- program instructions. The DMA controller performs DMA width for interprocessor communication, including: transfers between: • Up to eight DSPs on a common bus • Internal memory and external memory and memory- • On-chip arbitration for glueless multiprocessing mapped peripherals • Link ports for point-to-point communication • Internal memory of other DSPs on a common bus, a host processor, or link port I/O The external port and link ports provide integrated, glueless multiprocessing support. • External memory and external peripherals or link port I/O The external port supports a unified address space (see Figure 3) • External bus master and internal memory or link port I/O that enables direct interprocessor accesses of each The DMA controller provides a number of additional features. ADSP-TS101S processor’s internal memory and registers. The The DMA controller supports flyby transfers. Flyby operations DSP’s on-chip distributed bus arbitration logic provides simple, only occur through the external port (DMA Channel 0) and do glueless connection for systems containing up to eight ADSP- not involve the DSP’s core. The DMA controller acts as a con- TS101S processors and a host processor. Bus arbitration has a duit to transfer data from one external device to another rotating priority. Bus lock supports indivisible read-modify- through external memory. During a transaction, the DSP: write sequences for semaphores. A bus fairness feature prevents one DSP from holding the external bus too long. • Relinquishes the external data bus The DSP’s four link ports provide a second path for interproces- • Outputs addresses, memory selects (MS1–0, MSSD, RAS, sor communications with throughput of 1G bytes per second. CAS, and SDWE) and the FLYBY, IOEN, and RD/WR The cluster bus provides 800M bytes per second throughput— strobes with a total of 1.8G bytes per second interprocessor bandwidth. • Responds to ACK
SDRAM Controller
DMA chaining is also supported by the DMA controller. DMA chaining operations enable applications to automatically link The SDRAM controller controls the ADSP-TS101S processor’s one DMA transfer sequence to another for continuous trans- transfers of data to and from synchronous DRAM (SDRAM). mission. The sequences can occur over different DMA channels The throughput is 32 or 64 bits per SCLK cycle using the exter- and have different transmission attributes. nal port and SDRAM control pins. Rev. D | Page 7 of 45 | April 2021 Document Outline TigerSHARC Embedded Processor Features Benefits Table of Contents Revision History General Description Dual Compute Blocks Data Alignment Buffer (DAB) Dual Integer ALUs (IALUs) Program Sequencer Interrupt Controller Flexible Instruction Set On-Chip SRAM Memory External Port (Off-Chip Memory/Peripherals Interface) Host Interface Multiprocessor Interface SDRAM Controller EPROM Interface DMA Controller Link Ports Timer and General-Purpose I/O Reset and Booting Low Power Operation Clock Domains Output Pin Drive Strength Control Power Supplies Filtering Reference Voltage and Clocks Development Tools Designing an Emulator-Compatible DSP Board (Target) Additional Information Pin Function Descriptions Pin States at Reset Pin Definitions Strap Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Caution Timing Specifications General AC Timing Link Ports Data Transfer and Token Switch Timing Output Drive Currents Test Conditions Output Disable Time Output Enable Time Capacitive Loading Environmental Conditions Thermal Characteristics PBGA Pin Configurations Outline Dimensions Surface-Mount Design Ordering Guide