Datasheet ADSP-TS101S (Analog Devices)

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TigerSHARC Embedded Processor ADSP-TS101S FEATURES BENEFITS 300 MHz, 3.3 ns instruction cycle rate Provides high performance Static Superscalar DSP opera- 6M bits of internal—on-chip—SRAM memory tions, optimized for telecommunications infrastructure 19 mm × 19 mm (484-ball) CSP-BGA or 27 mm × 27 mm and other large, demanding multiprocessor DSP (625-ball) PBGA package applications Dual computation blocks—each containing an ALU, a multi- Performs exceptionally well on DSP algorithm and I/O bench- plier, a shifter, and a register file marks (see benchmarks in Table 1 and Table 2) Dual integer ALUs, providing data addressing and pointer Supports low overhead DMA transfers between internal manipulation memory, external memory, memory-mapped peripherals, Integrated I/O includes 14-channel DMA controller, external link ports, other DSPs (multiprocessor), and host port, 4 link ports, SDRAM controller, programmable flag processors pins, 2 timers, and timer expired pin for system integration Eases DSP programming through extremely flexible instruc- 1149.1 IEEE compliant JTAG test access port for on-chip tion set and high-level language-friendly DSP architecture emulation Enables scalable multiprocessing systems with low commu- On-chip arbitration for glueless multiprocessing with up to nications overhead 8 TigerSHARC processors on a bus COMPUTATIONAL BLOCKS PROGRAM SEQUENCER DATA ADDRESS GENERATION INTERNAL MEMORY 6 JTAG PORT PC BTB IRQ MEMORY MEMORY MEMORY SHIFTER INTEGER 32 32 INTEGER M0 M1 M2 J ALU K ALU 64K × 32 64K × 32 64K × 32 ADDR IAB 32 × 32 32 × 32 SDRAM CONTROLLER FETCH ALU A D A D A D MULTIPLIER EXTERNAL PORT 32 M0 ADDR X MULTIPROCESSOR M0 DATA REGISTER 128 INTERFACE FILE 32 32 × 32 HOST INTERFACE 32 ADDR M1 ADDR 128 128 INPUT FIFO 64 M1 DATA 128 DAB OUTPUT BUFFER DATA DAB 32 M2 ADDR OUTPUT FIFO 128 M2 DATA CNTRL 128 128 CLUSTER BUS I/O ADDRESS 32 ARBITER Y REGISTER I/O PROCESSOR 3 FILE 32 × 32 L0 8 DMA LINK PORT 3 CONTROLLER CONTROLLER MULTIPLIER L1 8 DMA ADDRESS LINK 32 256 256 LINK DATA 3 PORTS ALU DMA DATA L2 8 CONTROL/ CONTROL/ STATUS/ STATUS/ 3 SHIFTER TCBs BUFFERS L3 8
Figure 1. Functional Block Diagram TigerSHARC and the TigerSHARC logo are registered trademarks of Analog Devices, Inc.
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Document Outline TigerSHARC Embedded Processor Features Benefits Table of Contents Revision History General Description Dual Compute Blocks Data Alignment Buffer (DAB) Dual Integer ALUs (IALUs) Program Sequencer Interrupt Controller Flexible Instruction Set On-Chip SRAM Memory External Port (Off-Chip Memory/Peripherals Interface) Host Interface Multiprocessor Interface SDRAM Controller EPROM Interface DMA Controller Link Ports Timer and General-Purpose I/O Reset and Booting Low Power Operation Clock Domains Output Pin Drive Strength Control Power Supplies Filtering Reference Voltage and Clocks Development Tools Designing an Emulator-Compatible DSP Board (Target) Additional Information Pin Function Descriptions Pin States at Reset Pin Definitions Strap Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Caution Timing Specifications General AC Timing Link Ports Data Transfer and Token Switch Timing Output Drive Currents Test Conditions Output Disable Time Output Enable Time Capacitive Loading Environmental Conditions Thermal Characteristics PBGA Pin Configurations Outline Dimensions Surface-Mount Design Ordering Guide