Datasheet ADSP-TS101S (Analog Devices) - 5

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ADSP-TS101S
The IALUs have hardware support for circular buffers, bit
Flexible Instruction Set
reverse, and zero-overhead looping. Circular buffers facilitate The 128-bit instruction line, which can contain up to four 32-bit efficient programming of delay lines and other data structures instructions, accommodates a variety of parallel operations for required in digital signal processing, and they are commonly concise programming. For example, one instruction line can used in digital filters and Fourier transforms. Each IALU pro- direct the DSP to conditionally execute a multiply, an add, and a vides registers for four circular buffers, so applications can set subtract in both computation blocks while it also branches to up a total of eight circular buffers. The IALUs handle address another location in the program. Some key features of the pointer wraparound automatically, reducing overhead, increas- instruction set include: ing performance, and simplifying implementation. Circular buffers can start and end at any memory location. • Enhanced instructions for communications infrastructure to govern trellis decoding (for example, Viterbi and turbo Because the IALU’s computational pipeline is one cycle deep, in decoders) and despreading via complex correlations most cases, integer results are available in the next cycle. Hard- ware (register dependency check) causes a stall if a result is • Algebraic assembly language syntax unavailable in a given cycle. • Direct support for all DSP, imaging, and video arithmetic types, eliminating hardware modes
PROGRAM SEQUENCER
• Branch prediction encoded in instruction, enables zero- The ADSP-TS101S processor’s program sequencer supports: overhead loops • A fully interruptible programming model with flexible pro- • Parallelism encoded in instruction line gramming in assembly and C/C++ languages; handles hardware interrupts with high throughput and no aborted • Conditional execution optional for all instructions instruction cycles. • User-defined, programmable partitioning between pro- • An eight-cycle instruction pipeline—three-cycle fetch pipe gram and data memory and five-cycle execution pipe—with computation results
ON-CHIP SRAM MEMORY
available two cycles after operands are available. The ADSP-TS101S has 6M bits of on-chip SRAM memory, • The supply of instruction fetch memory addresses; the divided into three blocks of 2M bits (64K words  32 bits). Each sequencer’s instruction alignment buffer (IAB) caches up block—M0, M1, and M2—can store program, data, or both, so to five fetched instruction lines waiting to execute; the pro- applications can configure memory to suit specific needs. Plac- gram sequencer extracts an instruction line from the IAB ing program instructions and data in different memory blocks, and distributes it to the appropriate core component for however, enables the DSP to access data while performing an execution. instruction fetch. • The management of program structures and determination The DSP’s internal and external memory (Figure 3) is organized of program flow according to JUMP, CALL, RTI, RTS into a unified memory map, which defines the location instructions, loop structures, conditions, interrupts, and (address) of all elements in the system. The memory map is software exceptions. divided into four memory areas—host space, external memory, • Branch prediction and a 128-entry branch target buffer multiprocessor space, and internal memory—and each memory (BTB) to reduce branch delays for efficient execution of space, except host memory, is subdivided into smaller memory conditional and unconditional branch instructions and spaces. zero-overhead looping; correctly predicted branches that Each internal memory block connects to one of the 128-bit- are taken occur with zero-to-two overhead cycles, over- wide internal buses—block M0 to bus MD0, block M1 to bus coming the three-to-six stage branch penalty. MD1, and block M2 to bus MD2—enabling the DSP to perform • Compact code without the requirement to align code in three memory transfers in the same cycle. The DSP’s internal memory; the IAB handles alignment. bus architecture provides a total memory bandwidth of 14.4G bytes per second, enabling the core and I/O to access
Interrupt Controller
eight 32-bit data words (256 bits) and four 32-bit instructions The DSP supports nested and non-nested interrupts. Each each cycle. The DSP’s flexible memory structure enables: interrupt type has a register in the interrupt vector table. Also, • DSP core and I/O access of different memory blocks in the each has a bit in both the interrupt latch register and the inter- same cycle rupt mask register. All interrupts are fixed as either level sensitive or edge sensitive, except the IRQ3–0 hardware inter- • DSP core access of all three memory blocks in parallel— rupts, which are programmable. one instruction and two data accesses The DSP distinguishes between hardware interrupts and soft- • Programmable partitioning of program and data memory ware exceptions, handling them differently. When a software • Program access of all memory as 32-, 64-, or 128-bit exception occurs, the DSP aborts all other instructions in the words—16-bit words with the DAB instruction pipe. When a hardware interrupt occurs, the DSP • Complete context switch in less than 20 cycles (66 ns) continues to execute instructions already in the instruction pipe. Rev. D | Page 5 of 45 | April 2021 Document Outline TigerSHARC Embedded Processor Features Benefits Table of Contents Revision History General Description Dual Compute Blocks Data Alignment Buffer (DAB) Dual Integer ALUs (IALUs) Program Sequencer Interrupt Controller Flexible Instruction Set On-Chip SRAM Memory External Port (Off-Chip Memory/Peripherals Interface) Host Interface Multiprocessor Interface SDRAM Controller EPROM Interface DMA Controller Link Ports Timer and General-Purpose I/O Reset and Booting Low Power Operation Clock Domains Output Pin Drive Strength Control Power Supplies Filtering Reference Voltage and Clocks Development Tools Designing an Emulator-Compatible DSP Board (Target) Additional Information Pin Function Descriptions Pin States at Reset Pin Definitions Strap Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Caution Timing Specifications General AC Timing Link Ports Data Transfer and Token Switch Timing Output Drive Currents Test Conditions Output Disable Time Output Enable Time Capacitive Loading Environmental Conditions Thermal Characteristics PBGA Pin Configurations Outline Dimensions Surface-Mount Design Ordering Guide