Datasheet ADIN1110 (Analog Devices) - 6

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ADIN1110 Preliminary Technical Data TIMING CHARACTERISTICS POWER-UP TIMING Table 3. Power Up Timing Parameter Description Min Typ Max Unit
tRAMP Power supply ramp time 40 ms t1 Minimum time interval to internal power good 1 20 43 ms t2 Hardware configuration latch time 6 8 14 μs t3 Management interface active 50 ms 1 The minimum time interval is referenced to the last supply to reach its rising threshold. There is no specific power supply sequencing required.
FUNCTIONAL POWER SUPPLY INTERNAL POWER GOOD HARDWARE MANAGEMENT STATE OFF RAMP & INITIALIZATION CONFIG LATCHED INTERFACE ACTIVE t3 tRAMP t1 AVDD_H, AVDD_L tRAMP DVDD_1P1 VDDIO tRAMP RESET_N PIN HARDWARE CONFIGURATION CONFIGURATION DUAL FUNCTION PINS LATCHED PINS ENABLED AS OUTPUTS t2
Figure 2. Power-Up Timing Rev. PrA | Page 6 of 73 Document Outline Features Applications General Description Functional Block Diagram Specifications Timing Characteristics Power-Up Timing SPI Serial Interface Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Theory of Operation Power Supply Domains MAC Interrupt (INT_N) Auto-Negotiation Transmit Amplitude Resolution Master/Slave Resolution MDI Interface Reset Operation Power-On Reset Hardware Reset Software Reset MAC Subsystem Reset PHY Subsystem Reset LED Link Link Status Pin Powerdown Modes Hardware Powerdown Mode Software Powerdown Mode Hardware Configuration Pins Hardware Configuration Pin Functions Software Powerdown after Reset Master/Slave Preference Transmit Amplitude 8-Bit SPI CRC Bringing Up 10BASE-T1L Links Unmanaged PHY Operation Managed PHY Operation Power-up and Reset Complete Configuring the Part for Linking Advertisement of Transmit Level Operating Mode Advertisement of Master/Slave Successful Completion of Auto-Negotiation Link Status On-Chip Diagnostics Loopback Modes PMA Loopback PCS Loopback MAC Interface Loopback MAC Interface Remote Loopback Host Processor Loopback Frame Generator and Checker Frame Generator and Checker used with Remote Loopback with two MAC-PHYs Test Modes Accessing the test modes Applications Information System Level Power Management Transmit Level = 1.0 V pk-pk Transmit Level = 2.4 V pk-pk Component Recommendations Crystal External Clock Input 802.1AS Support Internal Free-running Counter Syntonized Counter Waveform Generation on TS_TIMER Output Register Summary SPI Protocol MAC Frame - Transmit and Receive Timestamp Capture Tx Frame over SPI Rx Frame over SPI Frame Filtering on Receive Rx Priority Queues Statistics Counters Rx Drop FIFO Full Counter Frame Rx/Tx Errors SRAM ECC error SPI Error Tx FIFO Overflow error SPI Access to the PHY Registers MDIO PHY Address Determination PHY Registers Contents Recommended Register Operation Latch Low Registers IEEE Duplicated Registers Read Modify Write Operation SPI Register Details SPI Protocol Control Register MAC Status Register Mask Bits for Driving the Interrupt Pin Register Egress Timestamp Status Register Error Status Register Error Status Mask Register P1 MAC Rx Frame Size Register P1 MAC Receive Register MAC Rx Threshold Register MAC Tx Frame Size Register MAC Transmit Register Tx FIFO Space Register Transmit Threshold Register MAC Configuration Register MAC FIFO Clear Register Software Reset Register MDIO Command and Address Register MDIO Clause 45 Address Register MDIO Write Data Register MDIO Read Data Register FIFO Sizes Register MAC Address DA Filter Upper 16 Bits Registers MAC Address DA Filter Middle 16 Bits Registers MAC Address DA Filter Lower 16 Bits Registers MAC DA Filter Table Rule Registers P1 Rx Frame Count Register P1 Rx Broadcast Frame Count Register P1 Rx Multicast Frame Count Register P1 Rx Unicast Frame Count Register P1 Rx CRC Errored Frame Count Register P1 Rx Align Error Count Register P1 Rx Long/Short Frame Error Count Register P1 Rx PHY Error Count Register P1 Tx Frame Count Register P1 Tx Broadcast Frame Count Register P1 Tx Multicast Frame Count Register P1 Tx Unicast Frame Count Register P1 Rx Frames Dropped Due to FIFO Full Register P1 Rx Frames Dropped Due to Filtering Register P1 Transmit Inter Frame Gap Register P1 Receive Inter Frame Gap Register P1 Max Receive Frame Length Register P1 Min Receive Frame Length Register Timestamp Accumulator Addend Register Timestamp Accumulator Addend Register Timer Update Compare Register Timer Update Compare Register Seconds Counter Lower Register Seconds Counter Upper Register Nanoseconds Counter Register Nanoseconds Counter Register Timer Configuration Register High Period for TS_TIMER Register High Period for TS_TIMER Register Low Period for TS_TIMER Register Low Period for TS_TIMER Register Quantization Error Correction Register TS_TIMER Counter Start Time Lower Register TS_TIMER Counter Start Time Upper Register TS_CAPT Pin Timestamp Register 0 TS_CAPT Pin Timestamp Register 1 TS_CAPT Pin Timestamp Register 2 TS_CAPT Pin Timestamp Register 3 TS_CAPT Free Running Counter Register Lower TS_CAPT Free Running Counter Upper Register Captured Egress Timestamp A Lower Register Captured Egress Timestamp A Upper Register Captured Egress Timestamp B Lower Register Captured Egress Timestamp B Upper Register Captured Egress Timestamp C Lower Register Captured Egress Timestamp C Upper Register P1 Rx Low Priority FIFO Frame Count Register P1 Rx High Priority FIFO Frame Count Register Tx FIFO Frame Count Register Tx FIFO Valid Half Words Register P1 Low Priority Rx FIFO Valid Half Words Register P1 High Priority Rx FIFO Valid Half Words Register Scratch Registers PHY Register Details BASE-T1 PMA/PMD Extended Ability Register BASE-T1 PMA/PMD Control Register 10BASE-T1L PMA Control Register 10BASE-T1L PMA Status Register 10BASE-T1L Test Mode Control Register 10BASE-T1L PMA Link Status Register 10BASE-T1L PCS Control Register BASE-T1 Autonegotiation Control Register BASE-T1 Autonegotiation Status Register BASE-T1 Autonegotiation Advertisement [15:0] Register BASE-T1 Autonegotiation Advertisement [31:16] Register BASE-T1 Autonegotiation Advertisement [47:32] Register BASE-T1 Autonegotiation Link Partner Base Page Ability [15:0] Register BASE-T1 Autonegotiation Link Partner Base Page Ability [31:16] Register BASE-T1 Autonegotiation Link Partner Base Page Ability [47:32] Register BASE-T1 Autonegotiation Next Page Transmit [15:0] Register BASE-T1 Autonegotiation Next Page Transmit [31:16] Register BASE-T1 Autonegotiation Next Page Transmit [47:32] Register BASE-T1 Autonegotiation Link Partner Next Page Ability [15:0] Register BASE-T1 Autonegotiation Link Partner Next Page Ability [31:16] Register BASE-T1 Autonegotiation Link Partner Next Page Ability [47:32] Register Extra Autonegotiation Status Register Vendor Specific MMD 1 Device Identifier High Register Vendor Specific MMD 1 Device Identifier Low Register System Interrupt Status Register PHY Subsystem Interrupt Status Register System Interrupt Mask Register PHY Subsystem Interrupt Mask Register Frame Checker Enable Register Frame Checker Interrupt Enable Register Frame Checker Transmit Select Register Receive Error Count Register Frame Checker Count High Register Frame Checker Count Low Register Frame Checker Length Error Count Register Frame Checker Alignment Error Count Register Frame Checker Symbol Error Count Register Frame Checker Oversized Frame Count Register Frame Checker Undersized Frame Count Register Frame Checker Odd Nibble Frame Count Register Frame Checker Odd Preamble Packet Count Register Frame Checker False Carrier Count Register Frame Generator Enable Register Frame Generator Control/Restart Register Frame Generator Continuous Mode Enable Register Frame Generator Interrupt Enable Register Frame Generator Frame Length Register Frame Generator Number of Frames High Register Frame Generator Number of Frames Low Register Frame Generator Done Register MAC Interface Loopbacks Configuration Register Software Reset Register Software Power-down Control Register PHY Subsystem Reset Register PHY MAC Interface Reset Register System Status Register CRSM Diagnostics Clock Control Register LED Control Register PCB Layout Recommendations PHY Package Layout Component Placement Crystal Placement and Routing Outline Dimensions