Datasheet LM25149-Q1 (Texas Instruments) - 5

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LM25149-Q1 www.ti.com
SNVSBV6 – DECEMBER 2020
7 Specifications 7.1 Absolute Maximum Ratings
Over operating junction temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Pin voltage VIN to PGND –0.3 47 V Pin voltage SW to PGND –0.3 47 V Pin voltage SW to PGND transient < 20 ns –5 V Pin voltage CBOOT to SW –0.3 6.5 V Pin voltage CBOOT to SW, transient < 20 ns –5 V Pin voltage HO to SW, transient < 20 ns –5 V Pin voltage LO to PGND, transient < 20 ns –1.5 0.3 V Pin voltage EN/UVLO to PGND –0.3 47 V VCC, VCCX, VDDA, PG, FB, CNFG, PFM/SYNC, RT, EXTCOMP to Pin voltage –0.3 6.5 V AGND Pin voltage VOUT , ISNS+ –0.3 36 V
TION
Pin voltage VOUT to ISNS+ –0.3 0.3 V Pin voltage PGND to AGND –0.3 0.3 V
MA
Pin voltage AEFVDDA to AEFGND –0.3 5.5 V
R
Pin voltage INJ to AEFGND –0.3 5.5 V Pin voltage SEN to AEFGND –0.3 47 V Pin voltage AEFGND to AVSS –0.3 0.3 V TJ Operating junction temperature –40 150 °C Tstg Storage temperature –55 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
NCE INFO
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
A
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
V
reliability.
AD 7.2 ESD Ratings VALUE UNIT
Human body model (HBM), per AEC Q100-002 (1) ±2000 Corner pins (1, 2, 11, 12, 13, 14, 23, V(ESD) Electrostatic discharge ±750 V Charged device model (CDM), per AEC and 24) Q100-011 Other pins ±500 (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
Over operating junction temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN Input supply voltage range 3.5 42 V VOUT Output voltage range 0.8 36 V Pin voltage SW to PGND –0.3 42 V Pin voltage CBOOT to SW –0.3 5 5.25 V Pin voltage FB, EXTCOMP, RT to AGND –0.3 5.25 V Pin voltage EN to PGND –0.3 42 V Pin voltage VCC, VCCX, VDDA to PGND –0.3 5 5.25 V Pin voltage VOUT, ISNS+ to PGND –0.3 36 V PGND to AGND –0.3 0.3 V Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: LM25149-Q1 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Description (continued) 6 Pin Configuration and Functions 6.1 Wettable Flanks 7 Specifications 7.1 Absolute Maximum Ratings 7.2 ESD Ratings  7.3 Recommended Operating Conditions 7.4 Thermal Information 7.5 Electrical Characteristics 7.6 Active EMI Filter 8 Detailed Description 8.1 Overview 8.2 Functional Block Diagram 8.3 Feature Description 8.3.1 Input Voltage Range (VIN) 8.3.2 High-Voltage Bias Supply Regulator (VCC, VCCX, VDDA) 8.3.3 Enable (EN) 8.3.4 Power Good Monitor (PG) 8.3.5 Switching Frequency (RT) 8.3.6 Active EMI Filter 8.3.7 Dual Random Spread Spectrum (DRSS) 8.3.8 Soft-Start 8.3.9 Output Voltage Setpoint (FB) 8.3.10 Minimum Controllable On-Time 8.3.11 Error Amplifier and PWM Comparator (FB, EXTCOMP) 8.3.12 Slope Compensation 8.3.13 Inductor Current Sense (ISNS+, VOUT) 8.3.13.1 Shunt Current Sensing 8.3.13.2 Inductor DCR Current Sensing 8.3.14 Hiccup Mode Current Limiting 8.3.15 High-Side and Low-Side Gate Drivers (HO, LO) 8.3.16 Output Configurations (CNFG) 8.3.17 Single-Output Two-phase Operation 8.4 Device Functional Modes 8.4.1 Standby Modes 8.4.2 Pulse Frequency Modulation and Synchronization (PFM/SYNC) 8.4.3 Thermal Shutdown 9 Application and Implementation 9.1 Application Information 9.1.1 Power Train Components 9.1.1.1 Buck Inductor 9.1.1.2 Output Capacitors 9.1.1.3 Input Capacitors 9.1.1.4 Power MOSFETs 9.1.1.5 EMI Filter 9.1.2 Error Amplifier and Compensation 9.2 Typical Application 9.2.1 Design Requirements 9.2.2 Detailed Design Procedure 9.2.2.1 Custom Design With WEBENCH® Tools 9.2.2.2 Custom Design With Excel Quickstart Tool 9.2.2.3 Buck Inductor 9.2.2.4 Current-Sense Resistance 9.2.2.5 Output Capacitors 9.2.2.6 Input Capacitors 9.2.2.7 Frequency Set Resistor 9.2.2.8 Feedback Resistors 9.2.2.9 Compensation Components 9.2.2.10 Active EMI Components 9.2.3 Application Curves 10 Power Supply Recommendations 11 Layout 11.1 Layout Guidelines 11.1.1 Power Stage Layout 11.1.2 Gate-Drive Layout 11.1.3 PWM Controller Layout 11.1.4 Active EMI Layout 11.1.5 Thermal Design and Layout 11.1.6 Ground Plane Design 11.2 Layout Example 12 Device and Documentation Support 12.1 Device Support 12.1.1 Development Support 12.1.2 Custom Design With WEBENCH® Tools 12.2 Documentation Support 12.2.1 Related Documentation 12.2.1.1 PCB Layout Resources 12.2.1.2 Thermal Design Resources 12.3 Receiving Notification of Documentation Updates 12.4 Support Resources 12.5 Trademarks 12.6 Electrostatic Discharge Caution 12.7 Glossary 13 Mechanical, Packaging, and Orderable Information