Datasheet STFW4N150, STP4N150, STW4N150 (STMicroelectronics)

STFW4N150 STP4N150, STW4N150
N-channel 1500 V, 5 Ω, 4 A, PowerMESH™ Power MOSFET in TO-220, TO-247, TO-3PF
Features Type VDSS RDS(on) max ID Pw
STFW4N150 1500 V < 7 Ω 4 A 63 W STP4N150 1500 V < 7 Ω 4 A 160 W 3 2 1 3 2 STW4N150 1500 V < 7 Ω 4 A 160 W
TO-220
1
TO-247
■ 100% avalanche tested ■ Intrinsic capacitances and Qg minimized ■ High speed switching 3 2 1 ■ Fully isolated TO-3PF plastic packages
TO-3PF
■ Creepage distance path is 5.4 mm (typ.) for TO-3PF
Application Figure 1. Internal schematic diagram.
■ Switching applications $
Description
Using the well consolidated high voltage MESH OVERLAY™ process, STMicroelectronics has designed an advanced family of very high voltage ' Power MOSFETs with outstanding performances. The strengthened layout coupled with the company’s proprietary edge termination structure, gives the lowest R 3 DS(on) per area, unrivalled gate charge and switching characteristics. !-V
Table 1. Device summary Order codes Marking Package Packaging
STFW4N150 4N150 TO-3PF Tube STP4N150 P4N150 TO-220 Tube STW4N150 W4N150 TO-247 Tube July 2009 Doc ID 11262 Rev 9 1/15 www.st.com 15 Document Outline Figure 1. Internal schematic diagram. Table 1. Device summary 1 Electrical ratings Table 2. Absolute maximum ratings Table 3. Thermal data Table 4. Avalanche characteristics 2 Electrical characteristics Table 5. On/off states Table 6. Dynamic Table 7. Source drain diode 2.1 Electrical characteristics (curves) Figure 2. Safe operating area for TO-220 Figure 3. Thermal impedance for TO-220 Figure 4. Safe operating area for TO-3PF Figure 5. Thermal impedance for TO-3PF Figure 6. Safe operating area for TO-247 Figure 7. Thermal impedance for TO-247 Figure 8. Output characteristics Figure 9. Transfer characteristics Figure 10. Transconductance Figure 11. Static drain-source on resistance Figure 12. Gate charge vs gate-source voltage Figure 13. Capacitance variations Figure 14. Normalized gate threshold voltage vs temperature Figure 15. Normalized on resistance vs temperature Figure 16. Source-drain diode forward characteristics Figure 17. Normalized BVDSS vs temperature Figure 18. Maximum avalanche energy vs temperature 3 Test circuits Figure 19. Switching times test circuit for resistive load Figure 20. Gate charge test circuit Figure 21. Test circuit for inductive load switching and diode recovery times Figure 22. Unclamped inductive load test circuit Figure 23. Unclamped inductive waveform Figure 24. Switching time waveform 4 Package mechanical data 5 Revision history Table 8. Document revision history