Datasheet ADSP-BF700, 701, 702, 703, 704, 705, 706, 707 (Analog Devices) - 5

ADSP-BF700/701/702/703/704/705/706/707
The program sequencer controls the flow of instruction execu- The assembly language, which takes advantage of the proces- tion, including instruction alignment and decoding. For sor’s unique architecture, offers the following advantages: program flow control, the sequencer supports PC relative and • Seamlessly integrated DSP/MCU features are optimized for indirect conditional jumps (with dynamic branch prediction), both 8-bit and 16-bit operations. and subroutine calls. Hardware supports zero-overhead loop- ing. The architecture is fully interlocked, meaning that the • A multi-issue load/store modified-Harvard architecture, programmer need not manage the pipeline when executing which supports two 16-bit MAC or four 8-bit ALU + two instructions with data dependencies. load/store + two pointer updates per cycle. The address arithmetic unit provides two addresses for simulta- • All registers, I/O, and memory are mapped into a unified neous dual fetches from memory. It contains a multiported 4G byte memory space, providing a simplified program- register file consisting of four sets of 32-bit index, modify, ming model. length, and base registers (for circular buffering), and eight • Control of all asynchronous and synchronous events to the additional 32-bit pointer registers (for C-style indexed stack processor is handled by two subsystems: the core event manipulation). controller (CEC) and the system event controller (SEC). The Blackfin processor supports a modified Harvard architec- • Microcontroller features, such as arbitrary bit and bit-field ture in combination with a hierarchical memory structure. Level manipulation, insertion, and extraction; integer operations 1 (L1) memories are those that typically operate at the full pro- on 8-, 16-, and 32-bit data-types; and separate user and cessor speed with little or no latency. At the L1 level, the supervisor stack pointers. instruction memory holds instructions only. The data memory • Code density enhancements, which include intermixing of holds data, and a dedicated scratchpad data memory stores 16-bit and 32-bit instructions (no mode switching, no code stack and local variable information. segregation). Frequently used instructions are encoded In addition, multiple L1 memory blocks are provided, offering a in 16 bits. configurable mix of SRAM and cache. The memory manage- ment unit (MMU) provides memory protection for individual
PROCESSOR INFRASTRUCTURE
tasks that may be operating on the core and can protect system The following sections provide information on the primary registers from unintended access. infrastructure components of the ADSP-BF70x processor. The architecture provides three modes of operation: user mode,
DMA Controllers
supervisor mode, and emulation mode. User mode has restricted access to certain system resources, thus providing a The processor uses direct memory access (DMA) to transfer protected software environment, while supervisor mode has data within memory spaces or between a memory space and a unrestricted access to the system and core resources. peripheral. The processor can specify data transfer operations and return to normal processing while the fully integrated DMA
INSTRUCTION SET DESCRIPTION
controller carries out the data transfers independent of proces- The Blackfin processor instruction set has been optimized so sor activity. that 16-bit opcodes represent the most frequently used instruc- DMA transfers can occur between memory and a peripheral or tions, resulting in excellent compiled code density. Complex between one memory and another memory. Each memory-to- DSP instructions are encoded into 32-bit opcodes, representing memory DMA stream uses two channels, where one channel is fully featured multifunction instructions. The Blackfin proces- the source channel, and the second is the destination channel. sor supports a limited multi-issue capability, where a 32-bit All DMAs can transport data to and from all on-chip and off- instruction can be issued in parallel with two 16-bit instruc- chip memories. Programs can use two types of DMA transfers, tions, allowing the programmer to use many of the core descriptor-based or register-based. Register-based DMA allows resources in a single instruction cycle. the processor to directly program DMA control registers to ini- The Blackfin processor family assembly language instruction set tiate a DMA transfer. On completion, the control registers may employs an algebraic syntax designed for ease of coding and be automatically updated with their original setup values for readability. The instructions have been specifically tuned to pro- continuous transfer. Descriptor-based DMA transfers require a vide a flexible, densely encoded instruction set that compiles to set of parameters stored within memory to initiate a DMA a very small final memory size. The instruction set also provides sequence. Descriptor-based DMA transfers allow multiple fully featured multifunction instructions that allow the pro- DMA sequences to be chained together and a DMA channel can grammer to use many of the processor core resources in a single be programmed to automatically set up and start another DMA instruction. Coupled with many features more often seen on transfer after the current sequence completes. microcontrollers, this instruction set is very efficient when com- The DMA controller supports the following DMA operations. piling C and C++ source code. In addition, the architecture supports both user (algorithm/application code) and supervisor • A single linear buffer that stops on completion. (O/S kernel, device drivers, debuggers, ISRs) modes of opera- • A linear buffer with negative, positive, or zero stride length. tion, allowing multiple levels of access to core processor resources. • A circular, auto-refreshing buffer that interrupts when each buffer becomes full. Rev. D | Page 5 of 114 | February 2019 Document Outline Blackfin+ Core Embedded Processor Features Peripherals Features Memory Table of Contents Revision History General Description Blackfin+ Processor Core Instruction Set Description Processor Infrastructure DMA Controllers Event Handling Trigger Routing Unit (TRU) General-Purpose I/O (GPIO) Pin Interrupts Pin Multiplexing Memory Architecture Internal (Core-Accessible) Memory OTP Memory Static Memory Controller (SMC) Dynamic Memory Controller (DMC) I/O Memory Space Booting Security Features Security Features Disclaimer Processor Safety Features Multi-Parity-Bit-Protected L1 Memories ECC-Protected L2 Memories CRC-Protected Memories Memory Protection System Protection Watchpoint Protection Watchdog Bandwidth Monitor Signal Watchdogs Up/Down Count Mismatch Detection Fault Management Additional Processor Peripherals Timers Serial Ports (SPORTs) General-Purpose Counters Parallel Peripheral Interface (PPI) Serial Peripheral Interface (SPI) Ports SPI Host Port (SPIHP) UART Ports 2-Wire Controller Interface (TWI) Mobile Storage Interface (MSI) Controller Area Network (CAN) USB 2.0 On-the-Go Dual-Role Device Controller Housekeeping ADC (HADC) System Crossbars (SCB) Power and Clock Management System Crystal Oscillator and USB Crystal Oscillator Real-Time Clock Clock Generation Clock Out/External Clock Power Management Reset Control Unit Voltage Regulation System Debug System Watchpoint Unit Debug Access Port Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits ADSP-BF706 EZ-KIT Mini Blackfin Low Power Imaging Platform (BLIP) Software Add-Ins for CrossCore Embedded Studio Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-BF70x Detailed Signal Descriptions 184-Ball CSP_BGA Signal Descriptions GPIO Multiplexing for 184-Ball CSP_BGA 12 mm × 12 mm 88-Lead LFCSP (QFN) Signal Descriptions GPIO Multiplexing for 12 mm × 12 mm 88-Lead LFCSP (QFN) ADSP-BF70x Designer Quick Reference Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Internal Power Dissipation HADC HADC Electrical Characteristics HADC DC Accuracy HADC Timing Specifications Absolute Maximum Ratings ESD Sensitivity Timing Specifications Clock and Reset Timing Power-Up Reset Timing Asynchronous Read SMC Read Cycle Timing With Reference to SYS_CLKOUT Asynchronous Flash Read Asynchronous Page Mode Read Asynchronous Write SMC Write Cycle Timing With Reference to SYS_CLKOUT Asynchronous Flash Write All Accesses DDR2 SDRAM Clock and Control Cycle Timing DDR2 SDRAM Read Cycle Timing DDR2 SDRAM Write Cycle Timing Mobile DDR SDRAM Clock and Control Cycle Timing Mobile DDR SDRAM Read Cycle Timing Mobile DDR SDRAM Write Cycle Timing General-Purpose I/O Port Timing (GPIO) Timer Cycle Timing Up/Down Counter/Rotary Encoder Timing Debug Interface (JTAG Emulation Port) Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing Serial Peripheral Interface (SPI) Port—Open Drain Mode (ODM) Timing Serial Peripheral Interface (SPI) Port—SPI_RDY Timing Enhanced Parallel Peripheral Interface Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Controller Area Network (CAN) Interface Universal Serial Bus (USB) Mobile Storage Interface (MSI) Controller Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Capacitive Loading Environmental Conditions ADSP-BF70x 184-Ball CSP_BGA Ball Assignments (Numerical by Ball Number) ADSP-BF70x 12 mm × 12 mm 88-Lead LFCSP (QFN) Lead Assignments (Numerical by Lead Number) Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide