Datasheet LT6106 (Analog Devices) - 9

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APPLICATIONS INFORMATION Output Error Due to the Amplifier DC Offset
V+
Voltage, VOS
R – IN RSENSE R + E IN +IN –IN OUT(VOS) = VOS • ROUT R + – IN LOAD The DC offset voltage of the amplifier adds directly to the V+ V– value of the sense voltage, VSENSE. This is the dominant error of the system and it limits the low end of the dynamic OUT V range. The paragraph “Selection of External Current Sense LT6106 OUT ROUT Resistor” provides details. + – 6106 F04 RIN = RIN – RSENSE
Output Error Due to the Bias Currents, I + – Figure 4. Second Input R Minimizes Error Due to Input Bias Current B and IB
The bias current I + B flows into the positive input of the
Minimum Output Voltage
internal op amp. I – B flows into the negative input. The curves of the Output Voltage vs Input Sense Voltage ⎛ R ⎞ show the behavior of the LT6106 with low input sense E + SENSE – OUT(IBIAS) = ROUT I ⎜B • –IB ⎟ voltages. When VSENSE = 0V, the output voltage will always ⎝ RIN ⎠ be slightly positive, the result of input offset voltages and Assuming I + – of a small amount of quiescent current (0.7µA to 1.2µA) B ≅ IB = IBIAS, and RSENSE << RIN then: flowing through the output device. The minimum output EOUT(IBIAS) ≅ –ROUT • IBIAS voltage in the Electrical Characteristics table include both It is convenient to refer the error to the input: these effects. EIN(IBIAS) ≅ –RIN • IBIAS
Power Dissipation Considerations
For instance if IBIAS is 60nA and RIN is 1k, the input referred The power dissipated by the LT6106 will cause a small error is 60µV. Note that in applications where RSENSE ≅ increase in the die temperature. This rise in junction tem- R + IN, IB causes a voltage offset in RSENSE that cancels the perature can be calculated if the output current and the error due to I – B and EOUT(IBIAS) ≅ 0mV. In most applica- supply current are known. tions, RSENSE << RIN, the bias current error can be similarly reduced if an external resistor R + The power dissipated in the LT6106 due to the output IN = (RIN – RSENSE) is connected as shown in Figure 4. Under both conditions: signal is: – E + – P – V IN(IBIAS) = ±RIN • IOS; where IOS = IB – IB OUT = (VIN OUT) • IOUT – If the offset current, I Since V ≅ V+, P OS, of the LT6106 amplifier is 6nA, IN OUT ≅ (V+ – VOUT) • IOUT the 60µV error above is reduced to 6µV. The power dissipated due to the quiescent supply current is: Adding R + IN as described will maximize the dynamic PQ = IS • (V+ – V–) range of the circuit. For less sensitive designs, R + IN is The total power dissipated is the output dissipation plus not necessary. the quiescent dissipation:
Output Error Due to Gain Error
PTOTAL = POUT + PQ The LT6106 exhibits a typical gain error of –0.25% at 1mA The junction temperature is given by: output current. The primary source of gain error is due to the finite gain to the PNP output transistor, which results in TJ = TA + θJA • PTOTAL a small percentage of the current in RIN not appearing in the At the maximum operating supply voltage of 36V and the output load ROUT. maximum guaranteed output current of 1mA, the total Rev. C For more information www.analog.com 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Electrical Characteristics Pin Configuration Typical Performance Characteristics Pin Functions Block Diagram Applications Information Package Description Revision History Typical Application Related Parts