Datasheet AD8324 (Analog Devices) - 6

AD8324 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. Parameter Rating Table 5.
Supply Voltage, VCC 3.63 V
Model θJA Unit
Input Voltage 20-Lead QSOP 83.21 °C/W VIN+, VIN– 1.5 V p-p 20-Lead LFCSP 30.42 °C/W DATEN, SDATA, CLK, SLEEP, TXEN −0.5 V to +3.63 V 1 Thermal resistance measured on SEMI standard 4-layer board. Internal Power Dissipation 776 mW 2 Thermal resistance measured on SEMI standard 4-layer board, paddle Operating Temperature Range soldered to board. 20-Lead LFCSP −40°C to +85°C 20-Lead QSOP −25°C to +70°C
ESD CAUTION
Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering, 60 sec) 300°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. C | Page 6 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC) TIMING REQUIREMENTS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUIT APPLICATIONS INFORMATION GENERAL APPLICATIONS CIRCUIT DESCRIPTION GAIN PROGRAMMING FOR THE AD8324 INPUT BIAS, IMPEDANCE, AND TERMINATION OUTPUT BIAS, IMPEDANCE, AND TERMINATION POWER SUPPLY SIGNAL INTEGRITY LAYOUT CONSIDERATIONS INITIAL POWER-UP RAMP PIN AND BYP PIN FEATURES POWER SAVING FEATURES DISTORTION, ADJACENT CHANNEL POWER, AND DOCSIS UTILIZING DIPLEX FILTERS NOISE AND DOCSIS DIFFERENTIAL SIGNAL SOURCE DIFFERENTIAL SIGNAL FROM SINGLE-ENDED SOURCE SINGLE-ENDED SOURCE OUTLINE DIMENSIONS ORDERING GUIDE