Datasheet AD8324 (Analog Devices) - 5

Data Sheet AD8324 TIMING REQUIREMENTS
VCC = 3.3 V, tR = tF = 4 ns, fCLK = 8 MHz, unless otherwise noted.
Table 3. Parameter Min Typ Max Unit
Clock Pulse Width (tWH) 16.0 ns Clock Period (tC) 32.0 ns Setup Time SDATA vs. Clock (tDS) 5.0 ns Setup Time DATEN vs. Clock (tES) 15.0 ns Hold Time SDATA vs. Clock (tDH) 5.0 ns Hold Time DATEN vs. Clock (tEH) 3.0 ns Input Rise and Fall Times, SDATA, DATEN, Clock (tR, tF) 10 ns
Timing Diagrams tDS VALID DATA-WORD G1 SDATA VALID DATA-WORD G2 MSB . LSB tC tWH CLK tES tEH 8 CLOCK CYCLES DATEN GAIN TRANSFER (G1) GAIN TRANSFER (G2) t TXEN OFF tGS tCN ANALOG OUTPUT
03 0 -0-
SIGNAL AMPLITUDE (p-p)
39 043 Figure 3. Serial Interface Timing
VALID DATA BIT SDATA MSB MSB-1 MSB-2 tDS tDH CLK
04339-0-004 Figure 4. SDATA Timing Rev. C | Page 5 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC) TIMING REQUIREMENTS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUIT APPLICATIONS INFORMATION GENERAL APPLICATIONS CIRCUIT DESCRIPTION GAIN PROGRAMMING FOR THE AD8324 INPUT BIAS, IMPEDANCE, AND TERMINATION OUTPUT BIAS, IMPEDANCE, AND TERMINATION POWER SUPPLY SIGNAL INTEGRITY LAYOUT CONSIDERATIONS INITIAL POWER-UP RAMP PIN AND BYP PIN FEATURES POWER SAVING FEATURES DISTORTION, ADJACENT CHANNEL POWER, AND DOCSIS UTILIZING DIPLEX FILTERS NOISE AND DOCSIS DIFFERENTIAL SIGNAL SOURCE DIFFERENTIAL SIGNAL FROM SINGLE-ENDED SOURCE SINGLE-ENDED SOURCE OUTLINE DIMENSIONS ORDERING GUIDE