Datasheet AD8324 (Analog Devices) - 3

link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 link to page 4
Data Sheet AD8324 SPECIFICATIONS
TA = 25°C, VCC = 3.3 V, RL = RIN = 75 Ω, VIN (differential) = 27.5 dBmV, unless otherwise noted. The AD8324 is characterized using a 1:1 transformer1 at the device output.
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS Specified AC Voltage Output = 61 dBmV, maximum gain 27.5 dBmV Input Resistance Single-ended input 550 Ω Differential input 1100 Ω Input Capacitance 2 pF GAIN CONTROL INTERFACE Voltage Gain Range 58 59 60 dB Maximum Gain Gain code = 60 decimal code 32.5 33.5 34.5 dB Minimum Gain Gain code = 1 decimal code −26.5 −25.5 −24.5 dB Output Step Size2 0.6 1.0 1.4 dB/LSB Output Step Size Temperature Coefficient TA = –40°C to +85°C ±0.004 dB/°C OUTPUT CHARACTERISTICS Bandwidth (–3 dB) All gain codes (1 decimal code to 60 decimal 100 MHz codes) Bandwidth Roll-Off f = 65 MHz 1.7 dB 1 dB Compression Point3 Maximum gain, f = 10 MHz, output referred 19.6 21 dBm Minimum gain, f = 10 MHz, input referred 2.1 3.7 dBm Output Noise2 Maximum Gain f = 10 MHz 157 166 nV/√Hz Minimum Gain f = 10 MHz 1.3 1.5 nV/√Hz Transmit Disable f = 10 MHz 1.1 1.2 nV/√Hz Noise Figure2 Maximum Gain f = 10 MHz 15.5 16.0 dB Differential Output Impedance Transmit enable and transmit disable 75 ± 30%4 Ω OVERALL PERFORMANCE Second-Order Harmonic Distortion5, 3 f = 33 MHz, VOUT = 61 dBmV at maximum gain −66 −60 dBc f = 65 MHz, VOUT = 61 dBmV at maximum gain −58 −53 dBc Third-Order Harmonic Distortion (SFDR)5, 3 f = 21 MHz, VOUT = 61 dBmV at maximum gain −59 −57.5 dBc f = 65 MHz, VOUT = 61 dBmV at maximum gain −54 −52.5 dBc Adjacent Power Channel Ratio (APCR)2, 6 −61 −58 dBc Isolation (Transmit Disable)2 Maximum gain, f = 65 MHz −75 −70 dB POWER CONTROL Transmit Enable Settling Time Maximum gain, VIN = 0 2.5 µs Transmit Disable Settling Time Maximum gain, VIN = 0 3.8 µs Output Switching Transients3 Equivalent output = 31 dBmV 2.5 6 mV p-p Equivalent output = 61 dBmV 27 71 mV p-p Output Settling Due to Gain Change Minimum gain to maximum gain 60 ns Due to Input Step Change Maximum gain, VIN = 27.5 dBmV 30 ns Rev. C | Page 3 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC) TIMING REQUIREMENTS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUIT APPLICATIONS INFORMATION GENERAL APPLICATIONS CIRCUIT DESCRIPTION GAIN PROGRAMMING FOR THE AD8324 INPUT BIAS, IMPEDANCE, AND TERMINATION OUTPUT BIAS, IMPEDANCE, AND TERMINATION POWER SUPPLY SIGNAL INTEGRITY LAYOUT CONSIDERATIONS INITIAL POWER-UP RAMP PIN AND BYP PIN FEATURES POWER SAVING FEATURES DISTORTION, ADJACENT CHANNEL POWER, AND DOCSIS UTILIZING DIPLEX FILTERS NOISE AND DOCSIS DIFFERENTIAL SIGNAL SOURCE DIFFERENTIAL SIGNAL FROM SINGLE-ENDED SOURCE SINGLE-ENDED SOURCE OUTLINE DIMENSIONS ORDERING GUIDE