Datasheet ADPA7002CHIP (Analog Devices) - 6

ADPA7002CHIP Data Sheet INTERFACE SCHEMATICS GND
003
VGG1A, VGG1B
17236- 007 17236- Figure 3. GND Interface Schematic Figure 7. VGG1A and VGG1B Schematic
VREF
008 004
RFOUT
17236- 17236- Figure 4. VREF Interface Schematic Figure 8. RFOUT Interface Schematic
VDD1A, VDD2A, VDD3A, VDD1B, VDD2B, VDD3B VDET
005
RFIN
009 17236- 17236- Figure 5. VDET Interface Schematic Figure 9. VDD1A, VDD2A, VDD3A, VDD1B, VDD2B, and VDD3B Interface Schematic 006
RFIN
17236- Figure 6. RFIN Interface Schematic Rev. C | Page 6 of 23 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS 20 GHz TO 34 GHz FREQUENCY RANGE 34 GHz TO 44 GHz FREQUENCY RANGE ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS CONSTANT DRAIN CURRENT (IDD) OPERATION THEORY OF OPERATION ADPA7002CHIP ASSEMBLY AND CIRCUIT DIAGRAMS ALTERNATE ASSEMBLY DIAGRAM BIASING PROCEDURES BIASING THE ADPA7002CHIP WITH THE HMC980LP4E Application Circuit Setup Limiting VGATE to Meet ADPA7002CHIP VGGx AMR Requirement HMC980LP4E Bias Sequence Constant Drain Current Bias vs. Constant Gate Voltage Bias MOUNTING AND BONDING TECHNIQUES FOR MILLIMETER WAVE GAAS MMICS Handling Precautions Mounting Wire Bonding OUTLINE DIMENSIONS ORDERING GUIDE