Datasheet ADL9006CHIPS (Analog Devices) - 6
| Fabricante | Analog Devices |
| Descripción | 2 GHz to 28 GHz, GaAs, pHEMT, MMIC, Low Noise Amplifier |
| Páginas / Página | 16 / 6 — ADL9006CHIPS. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. … |
| Formato / tamaño de archivo | PDF / 547 Kb |
| Idioma del documento | Inglés |
ADL9006CHIPS. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. VDD. GND. VGG2. TOP VIEW. (CIRCUIT SIDE). RFOUT. RFIN
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ADL9006CHIPS Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 5 VDD GND 4 VGG2 6 ADL9006CHIPS GND TOP VIEW 3 (CIRCUIT SIDE) RFOUT 7 GND 2 RFIN 8 GND NC GND 1 10 9
002
NOTES 1. NC = NO CONNECT. SEE THE ASSEMBLY DIAGRAM, FIGURE 42, FOR PROPER BONDING.
20122- Figure 2. Pad Configuration
Table 8. Pad Function Descriptions Pad No. Mnemonic Description
1, 3, 6, 8, 9 GND Ground. The GND pads are connected to the die bottom using thru die vias. See the assembly diagram for proper bonding (see Figure 42). See Figure 5 for the interface schematic. 2 RFIN RF Input. RFIN is ac-coupled and matched to 50 Ω. See Figure 3 for the interface schematic. 4 VGG2 Gain Control. VGG2 is dc-coupled and accomplishes gain control by reducing the internal voltage and by becoming more negative. Attach bypass capacitors to VGG2 as shown in the assembly diagram (see Figure 42). Under normal operating conditions, VGG2 is left open. See Figure 4 for the interface schematic. 5 VDD Power Supply Voltage for the Amplifier. Connect a dc bias to provide quiescient drain current (IDQ). See Figure 6 for the interface schematic. 7 RFOUT RF Output. RFOUT is ac-coupled and matched to 50 Ω. See Figure 7 for the interface schematic. 10 NC No Connect. See the assembly diagram, Figure 42, for proper bonding. Die Bottom GND Die bottom must be connected to RF and dc ground. See Figure 5 for the interface schematic.
INTERFACE SCHEMATICS GND
003
RFIN
007 20122- 20122- Figure 3. RFIN Interface Schematic Figure 5. GND Interface Schematic
VDD VGG2
004 005 20122- 20122- Figure 4. VGG2 Interface Schematic Figure 6. VDD Interface Schematic
RFOUT
006 20122- Figure 7. RFOUT Interface Schematic Rev. 0 | Page 6 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS 2 GHz TO 14 GHz 14 GHz TO 22 GHz 22 GHz TO 28 GHz DC SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ELECTRONIC DISCHARGE (ESD) RATINGS ESD Ratings for ADL9006CHIPS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS SMALL SIGNAL RESPONSE LARGE SIGNAL RESPONSE THEORY OF OPERATION APPLICATIONS INFORMATION TYPICAL APPLICATION CIRCUIT MOUNTING AND BONDING TECHNIQUES FOR MILLIMETERWAVE GaAs MMICs Handling Precautions ASSEMBLY DIAGRAM OUTLINE DIMENSIONS ORDERING GUIDE
ADL9006CHIPS Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 5 VDD GND 4 VGG2 6 ADL9006CHIPS GND TOP VIEW 3 (CIRCUIT SIDE) RFOUT 7 GND 2 RFIN 8 GND NC GND 1 10 9
002
NOTES 1. NC = NO CONNECT. SEE THE ASSEMBLY DIAGRAM, FIGURE 42, FOR PROPER BONDING.
20122- Figure 2. Pad Configuration
Table 8. Pad Function Descriptions Pad No. Mnemonic Description
1, 3, 6, 8, 9 GND Ground. The GND pads are connected to the die bottom using thru die vias. See the assembly diagram for proper bonding (see Figure 42). See Figure 5 for the interface schematic. 2 RFIN RF Input. RFIN is ac-coupled and matched to 50 Ω. See Figure 3 for the interface schematic. 4 VGG2 Gain Control. VGG2 is dc-coupled and accomplishes gain control by reducing the internal voltage and by becoming more negative. Attach bypass capacitors to VGG2 as shown in the assembly diagram (see Figure 42). Under normal operating conditions, VGG2 is left open. See Figure 4 for the interface schematic. 5 VDD Power Supply Voltage for the Amplifier. Connect a dc bias to provide quiescient drain current (IDQ). See Figure 6 for the interface schematic. 7 RFOUT RF Output. RFOUT is ac-coupled and matched to 50 Ω. See Figure 7 for the interface schematic. 10 NC No Connect. See the assembly diagram, Figure 42, for proper bonding. Die Bottom GND Die bottom must be connected to RF and dc ground. See Figure 5 for the interface schematic.
INTERFACE SCHEMATICS GND
003
RFIN
007 20122- 20122- Figure 3. RFIN Interface Schematic Figure 5. GND Interface Schematic
VDD VGG2
004 005 20122- 20122- Figure 4. VGG2 Interface Schematic Figure 6. VDD Interface Schematic
RFOUT
006 20122- Figure 7. RFOUT Interface Schematic Rev. 0 | Page 6 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS 2 GHz TO 14 GHz 14 GHz TO 22 GHz 22 GHz TO 28 GHz DC SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ELECTRONIC DISCHARGE (ESD) RATINGS ESD Ratings for ADL9006CHIPS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS SMALL SIGNAL RESPONSE LARGE SIGNAL RESPONSE THEORY OF OPERATION APPLICATIONS INFORMATION TYPICAL APPLICATION CIRCUIT MOUNTING AND BONDING TECHNIQUES FOR MILLIMETERWAVE GaAs MMICs Handling Precautions ASSEMBLY DIAGRAM OUTLINE DIMENSIONS ORDERING GUIDE