link to page 19 link to page 19 link to page 19 link to page 19 link to page 19 link to page 19 ADL8111Data SheetINTERNAL AMPLIFIER STATE16161214812)4)BS11BS21100S22SE (dSE (dNN8–4ESPOESPO6R–8R45.5V–125.0V 4.5V–162–200012345678910 029 012345678 032 FREQUENCY (GHz) 20106- FREQUENCY (GHz) 20106- Figure 26. Broadband Gain and Return Loss vs. Frequency (100 MHz to 10 GHz), Figure 29. Gain vs Frequency Over VDD (100 MHz to 10 GHz), State = Internal Amplifier (Refer to Figure 76 for the Test Circuit) State = Internal Amplifier (Refer to Figure 76 for the Test Circuit) 161614141212))B10B10SE (dSE (dN8N8ESPO6ESPO6RR+85°C4+25°C+85°C4–40°C+25°C –40°C22000.010.020.030.040.050.060.070.080.090.10 030 012345678 033 FREQUENCY (GHz) 20106- FREQUENCY (GHz) 20106- Figure 27. Gain Over Temperature vs. Frequency (10 MHz to 100 MHz) Figure 30. Gain vs. Frequency Over Temperature (100 MHz to 10 GHz) State = Internal Amplifier (Refer to Figure 76 for the Test Circuit) State = Internal Amplifier (Refer to Figure 76 for the Test Circuit) 00+85°C–5–5+25°C –40°CB)B)dd((SSSSO–10O–10URN LURN LTT–15–15REREUTUT+85°CINP+25°CINP–20–40°C–20–25–250.010.020.030.040.050.060.070.080.090.10 031 012345678 034 FREQUENCY (GHz) 20106- FREQUENCY (GHz) 20106- Figure 28. Input Return Loss vs. Frequency (10 MHz to 100 MHz), Figure 31. Input Return Loss vs. Frequency Over Temperature (100 MHz to 8 GHz), State = Internal Amplifier (Refer to Figure 76 for the Test Circuit) State = Internal Amplifier (Refer to Figure 76 for the Test Circuit) Rev. 0 | Page 10 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE POWER DERATING CURVES ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS EXTERNAL BYPASS A STATE INTERNAL AMPLIFIER STATE INTERNAL BYPASS STATE EXTERNAL BYPASS B STATE TEST CIRCUITS THEORY OF OPERATION SIGNAL PATH STATES FOR DIGITAL CONTROL INPUTS APPLICATIONS INFORMATION RECOMMENDED BIAS SEQUENCING During Power-Up During Power-Down EVALUATION PCB EVALUATION BOARD SCHEMATIC OUTLINE DIMENSIONS ORDERING GUIDE