link to page 19 link to page 19 link to page 19 link to page 19 link to page 19 link to page 19 ADL8111Data Sheet00+85°C+85°C–5+25°C–5+25°C–40°CB)–40°CB)dd((SSSSOO–10–10URN LURN LTT–15RE–15REUTUTPINPUT O–20–20–25–25012345678 017 012345678 020 FREQUENCY (GHz) 20106- FREQUENCY (GHz) 20106- Figure 16. Input Return Loss Over Temperature vs. Frequency, Figure 19. Output Return Loss Over Temperature vs. Frequency, State = External Bypass A, Path = RFIN to OUT_A (Refer to Figure 75 for the State = External Bypass A, Path = IN_A to RFOUT (Refer to Figure 75 for the Test Circuit) Test Circuit) 00+85°C+85°C))–5+25°C–5+25°CdB–40°CdB–40°C((SSLOS–10LOSN–10NRRTUTUEERR–15–15TETETATAOFF S–20OFF S–20–25–25012345678 018 012345678 021 FREQUENCY (GHz) 20106- FREQUENCY (GHz) 20106- Figure 17. Off State Return Loss vs. Frequency Over Temperature, Figure 20. Off State Return Loss vs. Frequency Over Temperature, State = External Bypass A, Path = OUT_B (Refer to Figure 75 for the Test State = External Bypass A, Path = IN_B (Refer to Figure 75 for the Test Circuit) Circuit) 00RFIN TO OUT_B +85°CRFIN TO RFOUT +85°C–10RFIN TO OUT_B +25°C–10RFIN TO RFOUT +25°CRFIN TO OUT_B –40°CRFIN TO RFOUT –40°C–20–20))–30dB–30dB((–40TION–40TIONOLA–50OLA–50ISIS–60–60–70–70–80–80012345678 019 012345678 022 FREQUENCY (GHz) 20106- FREQUENCY (GHz) 20106- Figure 18. Isolation vs. Frequency Over Temperature, Figure 21. Isolation vs. Frequency Over Temperature, State = External Bypass A (Refer to Figure 75 for the Test Circuit) State = External Bypass A (Refer to Figure 75 for the Test Circuit) Rev. 0 | Page 8 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE POWER DERATING CURVES ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS EXTERNAL BYPASS A STATE INTERNAL AMPLIFIER STATE INTERNAL BYPASS STATE EXTERNAL BYPASS B STATE TEST CIRCUITS THEORY OF OPERATION SIGNAL PATH STATES FOR DIGITAL CONTROL INPUTS APPLICATIONS INFORMATION RECOMMENDED BIAS SEQUENCING During Power-Up During Power-Down EVALUATION PCB EVALUATION BOARD SCHEMATIC OUTLINE DIMENSIONS ORDERING GUIDE