link to page 24 Data SheetADL8111ABSOLUTE MAXIMUM RATINGS Table 5.POWER DERATING CURVESParameterRating5 VDD_PA +7 V dc VDD_SW Range −0.3 V to +3.7 V 0 VSS_SW Range −3.7 V to +0.3 V B) d (–5 Control Voltage (VA, VB) Range −0.3 V to VDD + 0.3 V INGRAT–10 RF Input Power (RFIN) − Internal Amplifier State 20 dBm RFIN − Internal Bypass, 31 dBm R DE E W–15 External Bypass A, External Bypass B O P RFIN (IN_A, OUT_A, IN_B, and OUT_B) 28 dBm –20 Termination Path (VDD_SW, VA, VB = 3.3 V, VSS = −3.3 V, TA = 85°C, and Frequency = 2 GHz) –250.010.11101001k10k 002 Hot Switch Power Level (IN_A, OUT_A, IN_B, 30 dBm FREQUENCY (MHz) 20106- and OUT_B), VDD_SW = 3.3 V, TA = 85°C, Figure 2. Power Derating for RFIN Port and Frequency = 2 GHz 2 Hot Switch Power Level (Internal Amplifier 20 dBm State) 0 Continuous Power Dissipation, P –2 DISS 0.61 W (TA = 85°C, Derate 6.8 mW/°C Above 85°C) B)–4d ( Channel Temperature 175°C –6ING Maximum Peak Reflow Temperature 260°C RAT–8 (Moisture Sensitivity Level 3, MSL3)1 R DE Storage Temperature Range −40°C to +125°C –10E W Operating Temperature Range −40°C to +85°C O –12P ESD Sensitivity (Human Body Model) Class 1B –14 (Passed ±750 V) –16 1 See the Ordering Guide section for additional information. –1810k100k1M10M100M1G10G 003 Stresses at or above those listed under Absolute Maximum FREQUENCY (Hz) 20106- Ratings may cause permanent damage to the product. This is a Figure 3. Power Derating for Terminated Path stress rating only; functional operation of the product at these 2 or any other conditions above those indicated in the operational 0 section of this specification is not implied. Operation beyond –2 the maximum operating conditions for extended periods may B)–4 affect product reliability. d (–6INGTHERMAL RESISTANCERAT–8 Thermal performance is directly linked to the printed circuit R DE –10E board (PCB) design and operating environment. Careful W O –12 attention to PCB thermal design is required. P–14 θJC is the junction to case thermal resistance. –16Table 6. Thermal Resistance–1810k100k1M10M100M1G10G 004 Package TypeθJCUnitFREQUENCY (Hz) 20106- CC-28-31 148 °C/W Figure 4. Power Derating for Hot Switching Power 1 θ ESD CAUTION JC was determined by simulation under the following conditions: the heat transfer is due solely to thermal conduction from the channel through the ground paddle to the PCB, and the ground paddle is held constant at an 85°C operating temperature. Rev. 0 | Page 5 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE POWER DERATING CURVES ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS EXTERNAL BYPASS A STATE INTERNAL AMPLIFIER STATE INTERNAL BYPASS STATE EXTERNAL BYPASS B STATE TEST CIRCUITS THEORY OF OPERATION SIGNAL PATH STATES FOR DIGITAL CONTROL INPUTS APPLICATIONS INFORMATION RECOMMENDED BIAS SEQUENCING During Power-Up During Power-Down EVALUATION PCB EVALUATION BOARD SCHEMATIC OUTLINE DIMENSIONS ORDERING GUIDE